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公开(公告)号：EP1292122A1
公开(公告)日：2003-03-12
申请号：EP02703937.9
申请日：2002-03-07
发明人： YAMATE, Kazunori
IPC分类号： H04N3/23
CPC分类号： H04N3/2335
摘要： A parabolic modulation circuit multiples a horizontal parabolic signal and a vertical modulation signal together, to amplitude-modulate the horizontal parabolic signal using the vertical modulation signal, and modulates the phase of the horizontal parabolic signal on the basis of the vertical modulation signal, to output the modulated horizontal parabolic signal to a correction current output amplifier. When an NS pincushion distortion on a screen of a CRT is asymmetrical, a horizontal parabolic signal generation circuit is so set as to generate an asymmetrical horizontal parabolic signal. A gull-wing distortion can be corrected by adjusting the value of n in an n-th power waveform generator in the horizontal parabolic signal generation circuit.
摘要翻译： 抛物线调制电路一起倍增水平抛物线信号和垂直调制信号，以使用垂直调制信号对水平抛物线信号进行幅度调制，并基于垂直调制信号调制水平抛物线信号的相位，以输出 调制的水平抛物线信号送到校正电流输出放大器。 当CRT屏幕上的NS枕形失真不对称时，设置水平抛物线信号发生电路以产生不对称的水平抛物线信号。 鸥翼失真可以通过调整水平抛物线信号发生电路中第n个功率波形发生器中的n值来校正。
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公开(公告)号：EP1115246A1
公开(公告)日：2001-07-11
申请号：EP00946275.5
申请日：2000-07-12
IPC分类号： H04N3/30
摘要： A primary winding of a transformer is serially connected to a horizontal deflection coil. An amplitude regulating circuit outputs a first correction voltage in response to a voltage generated on a secondary winding of the transformer. A phase regulating circuit regulates the phase of the first correction voltage output from the amplitude regulating circuit and outputs a second correction voltage. An addition circuit adds the second correction voltage to a sawtooth wave voltage generated by a sawtooth wave voltage generation circuit. A correction current output from an amplifier in response to the second correction voltage output from the phase regulating circuit cancels a current component generated on a vertical deflection coil by a horizontal deflection current.
摘要翻译： 变压器的初级绕组串联连接到水平偏转线圈。 振幅调节电路响应于在变压器的次级绕组上产生的电压输出第一校正电压。 相位调节电路调节从幅度调节电路输出的第一校正电压的相位，并输出第二校正电压。 加法电路将第二校正电压加到由锯齿波电压产生电路产生的锯齿波电压。 响应于从相位调节电路输出的第二校正电压从放大器输出的校正电流通过水平偏转电流抵消在垂直偏转线圈上产生的电流分量。
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公开(公告)号：EP0493607A1
公开(公告)日：1992-07-08
申请号：EP91913067.4
申请日：1991-07-17
发明人： YAMATE, Kazunori , DANMOTO, Keiichi
CPC分类号： H03L7/093 , H03L7/23 , H03M1/822 , H04J3/1676
摘要： A clock regenerating circuit for improving the SN ratio of a D/A converter of a PWM type, which comprises a first clock regenerating part (II) having a quartz-crystal (11a) and a voltage controlled oscillator (11b), and a second clock regenerating part (12) which generates an objective clock signal, multiplying the frequency of the output signal of the first clock regenerating part (11). The second clock regenerating part (12) comprises a phase comparator (22), a loop filter, a voltage controlled oscillator (26) of a resistance-capacitance type, and frequency demultiplier (25). Further, the loop filter comprises a second LPF (24) controlling the oscillating frequency of the voltage controlled oscillator (26) of a resistance-capacitance type, and a first filter (23) which has a cut-off frequency higher than that of the second LPF (24), and has a filter characteristic capable of cutting off the frequency components above the frequency of the output signal of the first clock regenerating part (11). Thus, unnecessary spectrum components are prevented from entering the D/A converter.
摘要翻译： 一种用于提高PWM类型的D / A转换器的SN比的时钟再生电路，其包括具有石英晶体（11a）的第一时钟再生部分（II）和压控振荡器（11b） 时钟再生部分（12），其生成目标时钟信号，将第一时钟再生部分（11）的输出信号的频率相乘。 第二时钟再生部分（12）包括相位比较器（22），环路滤波器，电阻电容型压控振荡器（26）和分频器（25）。 此外，环路滤波器包括控制电阻电容型的压控振荡器（26）的振荡频率的第二LPF（24）和具有比所述电压电容型的截止频率高的截止频率的第一滤波器（23） 第二LPF（24），并且具有能够切断高于第一时钟再生部（11）的输出信号的频率的频率分量的滤波器特性。 因此，防止不必要的频谱分量进入D / A转换器。
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公开(公告)号：EP1615193A1
公开(公告)日：2006-01-11
申请号：EP04727734.8
申请日：2004-04-15
发明人： YAMATE, Kazunori
CPC分类号： H05K1/148 , H05K3/0058 , H05K2201/10356 , H05K2201/10393
摘要： A flat-panel display unit is provided which includes: a PDP 10; an aluminum chassis 2 that is attached to the PDP 10; an upper data driver substrate 6 and a signal processing substrate 7 that are attached to the aluminum chassis 2; and a flexible cable 8 that connects the substrates 6, 7 electrically. Between the substrates 6, 7, a pressing plate 9 fixes at least one part of the flexible cable 8, so that the space between the flexible cable 8 and the aluminum chassis 2 remains unchanged. Thereby, a stray capacitor can be stably formed using the insulating material of the flexible cable 8, and a high-frequency noise can be effectively reduced.
摘要翻译： 提供了一种平板显示单元，包括：PDP 10; 连接到PDP 10的铝底盘2; 附接到铝底盘2的上数据驱动器基板6和信号处理基板7; 以及电连接基板6,7的柔性电缆8。 在基板6,7之间，压板9固定柔性电缆8的至少一部分，使得柔性电缆8和铝底盘2之间的空间保持不变。 从而，可以使用柔性电缆8的绝缘材料稳定地形成杂散电容器，并且可以有效地降低高频噪声。
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公开(公告)号：EP1496686A1
公开(公告)日：2005-01-12
申请号：EP03746484.9
申请日：2003-04-14
发明人： YAMATE, Kazunori
IPC分类号： H04N3/32
CPC分类号： H04N3/32
摘要： A video display apparatus comprises a luminance signal processing circuit, a color-difference signal processing circuit, an RGB matrix circuit, a CRT drive circuit, a plurality of VM coils, a plurality of scanning-speed modulation circuit blocks, a horizontal deflection circuit, a vertical deflection circuit, a horizontal deflection coil, and a vertical deflection coil. An electron beam emitted inside the CRT by the CRT drive circuit is scanned horizontally and vertically by the horizontal deflection coil and the vertical deflection coil. Velocity modulation currents are supplied to the plurality of VM coils by the plurality of scanning-speed modulation circuit blocks. This results in the generation of velocity modulation magnetic fields from the plurality of VM coils, thereby partially modulating the velocity of the horizontally scanned electron beam.
摘要翻译： 视频显示装置包括亮度信号处理电路，色差信号处理电路，RGB矩阵电路，CRT驱动电路，多个VM线圈，多个扫描速度调制电路块，水平偏转电路， 垂直偏转电路，水平偏转线圈和垂直偏转线圈。 通过CRT驱动电路在CRT内发射的电子束被水平偏转线圈和垂直偏转线圈水平和垂直扫描。 速度调制电流由多个扫描速度调制电路块提供给多个VM线圈。 这导致从多个VM线圈产生速度调制磁场，从而部分地调制水平扫描的电子束的速度。
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6.发明公开
公开(公告)号：EP1304869A1
公开(公告)日：2003-04-23
申请号：EP01950036.2
申请日：2001-07-23
CPC分类号： H04N3/2335
摘要： A write PLL circuit generates a write clock signal for writing a video signal into a line memory. A readout PLL circuit generates a read clock signal for reading out the video signal stored in the line memory. An inner pincushion distortion correction voltage generation circuit modulates a correction waveform in the horizontal scanning period of time by a correction waveform in the vertical scanning period of time, to generate an inner pincushion distortion correction waveform, and adds a DC correction pulse to the inner pincushion distortion correction waveform and outputs the inner pincushion distortion correction waveform as an inner pincushion distortion correction voltage. A capacitive coupling circuit superimposes the inner pincushion distortion correction voltage on an output voltage of a loop filter of the readout PLL circuit, and feeds the inner pincushion distortion correction voltage to a VCO as a control voltage.
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公开(公告)号：EP0493607B1
公开(公告)日：1997-03-05
申请号：EP91913067.4
申请日：1991-07-17
发明人： YAMATE, Kazunori , DANMOTO, Keiichi
CPC分类号： H03L7/093 , H03L7/23 , H03M1/822 , H04J3/1676
摘要： A clock regenerating circuit for improving the SN ratio of a D/A converter of a PWM type, which comprises a first clock regenerating part (11) having a quartz-crystal (11a) and a voltage controlled oscillator (11b), and a second clock regenerating part (12) which generates an objective clock signal, multiplying the frequency of the output signal of the first clock regenerating part (11). The second clock regenerating part (12) comprises a phase comparator (22), a loop filter, a voltage controlled oscillator (26) of a resistance-capacitance type, and frequency demultiplier (25). Further, the loop filter comprises a second LPF (24) controlling the oscillating frequency of the voltage controlled oscillator (26) of a resistance-capacitance type, and a first filter (23) which has a cut-off frequency higher than that of the second LPF (24), and has a filter characteristic capable of cutting off the frequency components above the frequency of the output signal of the first clock regenerating part (11). Thus, unnecessary spectrum components are prevented from entering the D/A converter.
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