公开(公告)号：EP1137012A2

公开(公告)日：2001-09-26

申请号：EP01106031.6

申请日：2001-03-12

申请人： MICROCHIP TECHNOLOGY INC.

发明人： Gerber, Donald S. ,  Shields, Jeffrey ,  Hewitt, Kent D. ,  Davies, David M

IPC分类号： G11C16/10 ,  G11C16/14

CPC分类号： G11C16/3427 ,  G11C16/10 ,  G11C16/14 ,  G11C16/3418 ,  G11C2216/28

摘要： A method of writing and selectively erasing bits in a selected group of memory cells that significantly reduces the likelihood of disturbing data stored in other, non-selected groups of memory cells is disclosed. The method varies the bias voltages applied to bit lines in unselected cells depending upon the selected or non-selected state of the cells. This reduces the voltage differential applied to the unselected cells, reducing the possibility of inadvertently causing unwanted changes in the amount of charge stored on the respective floating gates of the unselected cells. The method of the present invention improves electrical isolation between columns of cells without increasing the distance between the cells.

摘要翻译： 公开了一种写入和选择性地擦除所选存储器单元组中的位的方法，其显着地降低了存储在其它未选择的存储器单元组中的数据的干扰的可能性。 该方法根据所选择的或未选择的单元状态改变施加到未选择单元中的位线的偏置电压。 这降低了施加到未选择的单元的电压差，减少了无意中引起存储在未选择单元的相应浮动栅极上的电荷量的不期望的变化的可能性。 本发明的方法改善了电池列之间的电隔离，而不增加电池之间的距离。

公开(公告)号：EP1137012B1

公开(公告)日：2006-08-23

申请号：EP01106031.6

申请日：2001-03-12

申请人： MICROCHIP TECHNOLOGY INC.

发明人： Gerber, Donald S. ,  Shields, Jeffrey ,  Hewitt, Kent D. ,  Davies, David M

IPC分类号： G11C16/10 ,  G11C16/14

CPC分类号： G11C16/3427 ,  G11C16/10 ,  G11C16/14 ,  G11C16/3418 ,  G11C2216/28

公开(公告)号：EP1137012A3

公开(公告)日：2003-09-03

申请号：EP01106031.6

申请日：2001-03-12

申请人： MICROCHIP TECHNOLOGY INC.

发明人： Gerber, Donald S. ,  Shields, Jeffrey ,  Hewitt, Kent D. ,  Davies, David M

IPC分类号： G11C16/10 ,  G11C16/14

CPC分类号： G11C16/3427 ,  G11C16/10 ,  G11C16/14 ,  G11C16/3418 ,  G11C2216/28

摘要： A method of writing and selectively erasing bits in a selected group of memory cells that significantly reduces the likelihood of disturbing data stored in other, non-selected groups of memory cells is disclosed. The method varies the bias voltages applied to bit lines in unselected cells depending upon the selected or non-selected state of the cells. This reduces the voltage differential applied to the unselected cells, reducing the possibility of inadvertently causing unwanted changes in the amount of charge stored on the respective floating gates of the unselected cells. The method of the present invention improves electrical isolation between columns of cells without increasing the distance between the cells.