公开(公告)号：EP0862184B1

公开(公告)日：2004-01-14

申请号：EP98301296.4

申请日：1998-02-23

申请人： SHARP KABUSHIKI KAISHA

发明人： Ohta, Yoshiji

IPC分类号： G11C16/06

CPC分类号： G11C16/3445 ,  G11C8/10 ,  G11C16/344 ,  G11C2216/28

公开(公告)号：EP0558404A2

公开(公告)日：1993-09-01

申请号：EP93400468.0

申请日：1993-02-24

申请人： SONY CORPORATION

发明人： Arakawa, Hideki

IPC分类号： H01L27/115 ,  H01L29/788

CPC分类号： H01L29/7885 ,  G11C16/0416 ,  G11C16/08 ,  G11C16/26 ,  G11C2216/28 ,  H01L27/115 ,  H01L29/7883

摘要： The nonvolatile semiconductor memory uses a single floating gate transistor, wherein a control gate electrode (8) is negatively biased while a source region (2) is positively biased, and a writing operation is performed bit by bit by transferring electrons from the floating gate (5) into the source region through Fowler-Nordheim tunneling. And an erasing operation is performed by injecting channel hot electrons from the drain region (3) into the floating gate, or by injecting electrons from a substrate into the floating gate through Fowler-Nordheim tunneling. The source region is connected to an individual bit line, and the drain region to a common line so that over-erasing is averted.

摘要翻译： 非易失性半导体存储器使用单个浮置栅极晶体管，其中控制栅电极（8）在源极区域（2）被正偏置的同时被负偏置，并且通过从浮置栅极传送电子而逐位执行写入操作 5）通过Fowler-Nordheim隧道进入源区。 并且通过将沟道热电子从漏极区域（3）注入到浮动栅极中，或者通过Fowler-Nordheim隧道将电子从衬底注入到浮动栅极中来进行擦除操作。 源区域连接到单独的位线，并且漏极区域连接到公共线，使得避免过度擦除。

公开(公告)号：EP0862184A2

公开(公告)日：1998-09-02

申请号：EP98301296.4

申请日：1998-02-23

申请人： SHARP KABUSHIKI KAISHA

发明人： Ohta, Yoshiji

IPC分类号： G11C16/06

CPC分类号： G11C16/3445 ,  G11C8/10 ,  G11C16/344 ,  G11C2216/28

摘要： A verify operation is accurately collectively executed on all memory cells. In verify operation, first, the levels of a pre-charge signal φpre and a collective erase verify mode selection signal φaev are made to be "L", so that a common bit line 5 and all bit lines BL0 through BLm are individually charged with a pre-charge voltage Vpre. Thereafter, the level of the collective erase verify mode selection signal φaev is made to be "H" to connect the common bit line 5 to all the bit lines BL0 through BLm and a sense amplifier 8, and all word lines WL0 through WLn are selected by a row decoder circuit 2. Then, there is watched an event that the common bit line 5 is discharged and an output signal OUT of the sense amplifier 8 becomes "L" due to the existence of a non-erased memory cell in a memory cell array 1. In this case, the discharge of the common bit line 5 occurs when at least one non-erased memory cell transistor MT exists in the memory cell array 1, and therefore, the verify operation can be accurately collectively executed on all the memory cells.

摘要翻译： 甲验证操作被精确地设定共同执行的所有存储器单元。 在验证操作中，首先，一个预充电信号披预水平和集体擦除验证模式选择信号披AEV被做成“L”，所以没有公共位线5和所有位线BL0到BLm的单独 充有预充电电压Vpre。 存在后，集体擦除的电平验证模式选择信号披AEV被制成“H”到公共位线5连接到所有位线BL0到BLm的和读出放大器8，和所有字线WL0至WLn的 由行解码器电路2。然后选择，有观看事件没有公共位线5被排出，并输出信号OUT的读出放大器8变为“L”，由于未经擦除的存储器单元的一个中存在的 存储单元阵列1在这种情况下，发生公共位线的放电5当至少一个非擦除的存储器单元晶体管MT中存在的存储器单元阵列1中，并且因此，验证操作可以准确地对所有设定共同执行的 存储单元。

公开(公告)号：EP0052566A2

公开(公告)日：1982-05-26

申请号：EP81401794.3

申请日：1981-11-13

申请人： FAIRCHILD CAMERA & INSTRUMENT CORPORATION

发明人： Tickle, Andrew C.

IPC分类号： G11C17/00

CPC分类号： G11C16/3486 ,  G11C8/12 ,  G11C16/0408 ,  G11C16/08 ,  G11C16/16 ,  G11C16/3459 ,  G11C16/3468 ,  G11C2216/28

摘要： An electrically erasable programmable read-only memory (E 2 PROM) is provided which utilizes an inhibit voltage applied to unselected word lines during writing to prevent writing in unselected rows. In the preferred embodiment, each memory cell of the E 2 PROM array consists of a single floating gate field effect transistor. The E 2 PROM of the present invention provides for row erasure and single bit writing.

摘要翻译： 提供了一种电可擦除可编程只读存储器（E2PROM），其在写入期间利用施加到未选择字线的禁止电压以防止在未选择的行中写入。 在优选实施例中，E2PROM阵列的每个存储单元由单个浮栅场效应晶体管组成。 本发明的E2PROM提供行擦除和单位写入。

公开(公告)号：EP1137012A2

公开(公告)日：2001-09-26

申请号：EP01106031.6

申请日：2001-03-12

申请人： MICROCHIP TECHNOLOGY INC.

发明人： Gerber, Donald S. ,  Shields, Jeffrey ,  Hewitt, Kent D. ,  Davies, David M

IPC分类号： G11C16/10 ,  G11C16/14

CPC分类号： G11C16/3427 ,  G11C16/10 ,  G11C16/14 ,  G11C16/3418 ,  G11C2216/28

摘要： A method of writing and selectively erasing bits in a selected group of memory cells that significantly reduces the likelihood of disturbing data stored in other, non-selected groups of memory cells is disclosed. The method varies the bias voltages applied to bit lines in unselected cells depending upon the selected or non-selected state of the cells. This reduces the voltage differential applied to the unselected cells, reducing the possibility of inadvertently causing unwanted changes in the amount of charge stored on the respective floating gates of the unselected cells. The method of the present invention improves electrical isolation between columns of cells without increasing the distance between the cells.

摘要翻译： 公开了一种写入和选择性地擦除所选存储器单元组中的位的方法，其显着地降低了存储在其它未选择的存储器单元组中的数据的干扰的可能性。 该方法根据所选择的或未选择的单元状态改变施加到未选择单元中的位线的偏置电压。 这降低了施加到未选择的单元的电压差，减少了无意中引起存储在未选择单元的相应浮动栅极上的电荷量的不期望的变化的可能性。 本发明的方法改善了电池列之间的电隔离，而不增加电池之间的距离。

公开(公告)号：EP0903748A2

公开(公告)日：1999-03-24

申请号：EP98117243.0

申请日：1998-09-11

申请人： SANYO ELECTRIC Co., Ltd.

发明人： Yoneyama, Akira

IPC分类号： G11C16/06

CPC分类号： G11C16/3495 ,  G11C16/349 ,  G11C2216/28

摘要： A nonvolatile memory increases the number of times that data can be written and the length of time that data can be stored. A feature of the memory sets as a high reliability region a specific memory sector (for example, "0000" to "00FF") among a plurality of memory sectors. Within the high reliability sector, two or more memory cells are simultaneously written with the same data. During reading, the simultaneously written memory cells are read simultaneously, increasing current flow through the parallel current paths.

摘要翻译： 非易失性存储器增加了可以写入数据的次数以及可以存储数据的时间长度。 存储器的特征是将多个存储器扇区中的特定的存储器扇区（例如“0000”〜“00FF”）设定为高可靠性区域。 在高可靠性部分内，两个或更多个存储器单元被同时写入相同的数据。 在读取期间，同时写入的存储器单元被同时读取，增加电流流经并行电流路径。

公开(公告)号：EP1137012B1

公开(公告)日：2006-08-23

申请号：EP01106031.6

申请日：2001-03-12

申请人： MICROCHIP TECHNOLOGY INC.

发明人： Gerber, Donald S. ,  Shields, Jeffrey ,  Hewitt, Kent D. ,  Davies, David M

IPC分类号： G11C16/10 ,  G11C16/14

CPC分类号： G11C16/3427 ,  G11C16/10 ,  G11C16/14 ,  G11C16/3418 ,  G11C2216/28

公开(公告)号：EP0903748A3

公开(公告)日：2000-11-15

申请号：EP98117243.0

申请日：1998-09-11

申请人： SANYO ELECTRIC Co., Ltd.

发明人： Yoneyama, Akira

IPC分类号： G11C16/06

CPC分类号： G11C16/3495 ,  G11C16/349 ,  G11C2216/28

摘要： A nonvolatile memory increases the number of times that data can be written and the length of time that data can be stored. A feature of the memory sets as a high reliability region a specific memory sector (for example, "0000" to "00FF") among a plurality of memory sectors. Within the high reliability sector, two or more memory cells are simultaneously written with the same data. During reading, the simultaneously written memory cells are read simultaneously, increasing current flow through the parallel current paths.

摘要翻译： 非易失性存储器增加了可写入数据的次数以及可以存储数据的时间长度。 存储器的特征在多个存储器扇区中被设置为高可靠性区域的特定存储器扇区（例如，“0000”至“00FF”）。 在高可靠性扇区内，两个或多个存储单元同时写入相同的数据。 在读取期间，同时读取同时写入的存储单元，增加通过并联电流路径的电流。

公开(公告)号：EP0052566A3

公开(公告)日：1985-05-15

申请号：EP81401794

申请日：1981-11-13

申请人： FAIRCHILD CAMERA & INSTRUMENT CORPORATION

发明人： Tickle, Andrew C.

IPC分类号： G11C17/00

CPC分类号： G11C16/3486 ,  G11C8/12 ,  G11C16/0408 ,  G11C16/08 ,  G11C16/16 ,  G11C16/3459 ,  G11C16/3468 ,  G11C2216/28

摘要： An electrically erasable programmable read-only memory (E 2 PROM) is provided which utilizes an inhibit voltage applied to unselected word lines during writing to prevent writing in unselected rows. In the preferred embodiment, each memory cell of the E 2 PROM array consists of a single floating gate field effect transistor. The E 2 PROM of the present invention provides for row erasure and single bit writing.

摘要翻译： 提供了一种电可擦除可编程只读存储器（E2PROM），其在写入期间利用施加到未选择字线的禁止电压以防止在未选择的行中写入。 在优选实施例中，E2PROM阵列的每个存储单元由单个浮栅场效应晶体管组成。 本发明的E2PROM提供行擦除和单位写入。

公开(公告)号：EP0903748B1

公开(公告)日：2006-02-01

申请号：EP98117243.0

申请日：1998-09-11

申请人： SANYO ELECTRIC CO., LTD.

发明人： Yoneyama, Akira

IPC分类号： G11C16/06

CPC分类号： G11C16/3495 ,  G11C16/349 ,  G11C2216/28