公开(公告)号：EP1411360A2

公开(公告)日：2004-04-21

申请号：EP03029861.6

申请日：1998-02-11

Applicant: MICRON TECHNOLOGY, INC.

Inventor： Hembree, David R. ,  Farnworth, Warren M. ,  Akram, Salman ,  Wood, Alan G. ,  Doherty, C. Patrick ,  Krivy, Andy J.

IPC: G01R1/073 ,  G01R31/316

CPC classification number: G01R1/073 ,  G01R31/2886

Abstract: A probe card (10) for testing semiconductor wafers (12), and a method for testing wafers (12) using the probe card (10) are provided. The probe card (10) includes an interconnect substrate (16) having contact members (20) for establishing electrical communication with contact locations (15) on the wafer (12). The probe card (10) also includes a membrane (18) for physically and electrically connecting the interconnect substrate (16) to the testing apparatus (78), and a compressible member (28) for cushioning the pressure exerted on the interconnect substrate (16) by the testing apparatus (78). An indentation configured to retain bumped contacts (15B) of the wafers is formed in the substrate (16).

公开(公告)号：EP1411360A3

公开(公告)日：2004-04-28

申请号：EP03029861.6

申请日：1998-02-11

Applicant: MICRON TECHNOLOGY, INC.

Inventor： Hembree, David R. ,  Farnworth, Warren M. ,  Akram, Salman ,  Wood, Alan G. ,  Doherty, C. Patrick ,  Krivy, Andy J.

IPC: G01R1/073 ,  G01R31/316

CPC classification number: G01R1/073 ,  G01R31/2886

Abstract: A probe card (10) for testing semiconductor wafers (12), and a method for testing wafers (12) using the probe card (10) are provided. The probe card (10) includes an interconnect substrate (16) having contact members (20) for establishing electrical communication with contact locations (15) on the wafer (12). The probe card (10) also includes a membrane (18) for physically and electrically connecting the interconnect substrate (16) to the testing apparatus (78), and a compressible member (28) for cushioning the pressure exerted on the interconnect substrate (16) by the testing apparatus (78). An indentation configured to retain bumped contacts (15B) of the wafers is formed in the substrate (16).

Abstract translation: 探针卡（10）用于半导体晶片（12）的测试，半导体晶片（12）具有多个具有多个接触位置的半导体晶片。 晶圆支撑电路朝上，与探头接触。 探针卡包括互连基底（16）和膜（18）。 衬底包括被配置为接触半导体晶片的接触位置的接触构件（20）的图案。 膜将互连基板物理和电连接到安装到测试端口的探针卡夹具（22）。 膜安装板（24）将膜固定到固定装置上。 力施加机构（32）和弹簧加载力施加构件（34）与卡相关联。

公开(公告)号：EP1411359A1

公开(公告)日：2004-04-21

申请号：EP03029860.8

申请日：1998-02-11

Applicant: MICRON TECHNOLOGY, INC.

Inventor： Hembree, David R. ,  Farnworth, Warren M. ,  Akram, Salman ,  Wood, Alan G. ,  Doherty, C. Patrick ,  Krivy, Andy J.

IPC: G01R1/073 ,  G01R31/316

CPC classification number: G01R1/073 ,  G01R31/2886

Abstract: A probe card (10) for testing semiconductor wafers (12), and a method and system (82) for testing wafers (12) using the probe card (10) are provided. The probe card (10) includes an interconnect-substrate (16) having contact members (20) for establishing electrical communication with contact locations (15) on the wafer (12). The probe card (10) also includes a membrane (18) for physically and electrically connecting the interconnect-substrate (16) to the testing apparatus (78), and a compressible member (28) for cushioning the pressure exerted on the interconnect-substrate (16) by the testing apparatus (78).

Abstract translation: 提供了用于测试半导体晶片（12）的探针卡（10）以及用于使用探针卡（10）测试晶片（12）的方法和系统（82）。 探针卡（10）包括具有用于与晶片（12）上的接触位置（15）建立电连接的接触构件（20）的互连衬底（16）。 探针卡（10）还包括用于将互连基板（16）物理地和电气地连接到测试装置（78）的膜（18），以及用于缓冲施加在互连基板上的压力的可压缩构件（28） （16）通过测试装置（78）。