公开(公告)号：EP1691206A3

公开(公告)日：2006-08-30

申请号：EP06075592.3

申请日：1996-04-30

Applicant: MICRON TECHNOLOGY, INC.

Inventor： Wood, Alan G. ,  Farnworth, Warren M. ,  Akram, Salman ,  Hembree, David R.

IPC: G01R31/02 ,  G01R1/073 ,  G01R31/28 ,  G01R1/04 ,  H01L21/66

CPC classification number: G01R1/07314 ,  G01R1/0433 ,  G01R1/0466 ,  G01R1/0483 ,  G01R3/00 ,  G01R31/2863 ,  G01R31/2886 ,  G01R31/2889 ,  G01R31/2893 ,  H01L21/6835 ,  H01L22/20 ,  H01L23/13 ,  H01L23/49816 ,  H01L23/49838 ,  H01L24/48 ,  H01L24/80 ,  H01L24/85 ,  H01L2224/16145 ,  H01L2224/48 ,  H01L2224/85001 ,  H01L2224/85205 ,  H01L2225/06562 ,  H01L2924/00014 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01014 ,  H01L2924/01028 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01039 ,  H01L2924/01042 ,  H01L2924/01074 ,  H01L2924/01077 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/01087 ,  H01L2924/014 ,  H01L2924/09701 ,  H01L2924/14 ,  H01L2924/15151 ,  H01L2924/15174 ,  H01L2924/181 ,  H01L2924/19041 ,  H01L2924/30105 ,  H05K3/0058 ,  H05K3/0067 ,  H05K3/4007 ,  H05K3/423 ,  H05K2201/0133 ,  H05K2201/0347 ,  H05K2201/0367 ,  H05K2201/0394 ,  H05K2201/09481 ,  H05K2201/09563 ,  H05K2203/0307 ,  H05K2203/0723 ,  H01L2224/78 ,  H01L2224/45099 ,  H01L2224/05599 ,  H01L2924/00

Abstract: A method and apparatus for testing unpackaged semiconductor dice includes a mother board (10) and a plurality of interconnects (12) mounted on the mother board (10) and adapted to establish a temporary electrical connection with the dice (14). The interconnects (12) can be formed with a silicon substrate (20) and raised contact members (16) for contacting the bond pads (22) of a die (14). Alternately the interconnects (16) can be formed with micro bump contact members (16) mounted on an insulating film (74). The mother board (10) allows each die (14) to be tested separately for speed and functionality and to also be burn-in tested in parallel using standard burn-in ovens. In an alternate embodiment testing is performed using a mother board/daughter board arrangement. Each daughter board (82) includes interconnects (12) that allow the dice (14) to be tested individually for speed and functionality. Multiple daughter boards (82) can then be mounted to the mother board (10) for burn-in testing using standard burn-in ovens.

Abstract translation: 用于测试未封装半导体晶片的方法和装置包括安装在母板（10）上的母板（10）和多个互连（12），并适于建立与芯片（14）的临时电连接。 互连（12）可以形成有用于接触管芯（14）的接合焊盘（22）的硅衬底（20）和凸起的接触构件（16）。 或者，互连（16）可以形成有安装在绝缘膜（74）上的微凸块接触构件（16）。 母板（10）允许每个模具（14）单独测试速度和功能，并且还可以使用标准老化炉并行测试。 在替代实施例中，使用母板/子板布置进行测试。 每个子板（82）包括允许骰子（14）单独测试速度和功能的互连（12）。 然后可以将多个子板（82）安装到母板（10）上，以使用标准老化烤箱进行老化测试。

公开(公告)号：EP1251550B1

公开(公告)日：2005-03-30

申请号：EP02013585.1

申请日：1995-04-17

Applicant: MICRON TECHNOLOGY, INC.

Inventor： Farnworth, Warren M. ,  Folaron, Jennifer L. ,  Folaron, Robert J. ,  Hembree, David R. ,  Jacobson, John O. ,  Nelson, Jay C. ,  Warren, Lelan D.

IPC: H01L21/00 ,  H05K13/08

CPC classification number: H01L21/67276 ,  G01R31/2851 ,  G01R31/2886 ,  G01R31/2893 ,  G01R31/311 ,  H01L21/67126 ,  H01L21/67242 ,  H01L21/67259 ,  H01L21/681 ,  H01L24/74 ,  H01L2924/12042 ,  H01L2924/14 ,  H05K13/08 ,  Y10T29/49004 ,  Y10T29/49131 ,  Y10T29/53174 ,  Y10T29/53178 ,  H01L2924/00

公开(公告)号：EP1251550A1

公开(公告)日：2002-10-23

申请号：EP02013585.1

申请日：1995-04-17

Applicant: MICRON TECHNOLOGY, INC.

Inventor： Farnworth, Warren M. ,  Folaron, Jennifer L. ,  Folaron, Robert J. ,  Hembree, David R. ,  Jacobson, John O. ,  Nelson, Jay C. ,  Warren, Lelan D.

IPC: H01L21/00 ,  H05K13/08

CPC classification number: H01L21/67276 ,  G01R31/2851 ,  G01R31/2886 ,  G01R31/2893 ,  G01R31/311 ,  H01L21/67126 ,  H01L21/67242 ,  H01L21/67259 ,  H01L21/681 ,  H01L24/74 ,  H01L2924/12042 ,  H01L2924/14 ,  H05K13/08 ,  Y10T29/49004 ,  Y10T29/49131 ,  Y10T29/53174 ,  Y10T29/53178 ,  H01L2924/00

Abstract: An apparatus for automatically positioning electronic die within temporary packages to enable continuity testing and the like between the die bond pads and the temporary package electrical interconnects is provided. The apparatus includes a robot having a programmable robot arm with a gripper assembly, die and lid feeder stations, a die inverter, and a plurality of cameras or image producers. The cameras take several pictures of the die and temporary packages to precisely align the die bond pads with the temporary package electrical interconnects. A predetermined assembly position is located along a conveyor that conveys a carrier between a first position, corresponding to an inlet, and a second position, corresponding to an outlet. The die, a restraining device and temporary package are assembled at the predetermined assembly position and tested for continuity therebetween. The apparatus further includes a fifth camera which locates the die at a wafer handler. The apparatus has a control mechanism including a microprocessor and associated program routines that selectively control the robot arm (i) to move the gripper assembly to the lid feeder station to pick up a lid, (ii) to move the gripper assembly along with the lid to pick up the die following photographing by the rough die camera, (iii) to move the gripper assembly along with the lid and the die to a position to be photographed by the fine die camera, and (iv) to move the lid and the die to the predetermined assembly position located along the conveyor. The method and apparatus may also be used for disassembly.

Abstract translation: 提供了一种用于临时包内自动定位电子启用连续性测试和管芯接合焊盘和所述临时封装电互连件之间的装置等。 该装置包括具有一个可编程的机器人臂与夹持器组件，该盖和馈线站，一个是逆变器，和摄像机或图像生产者的多个机器人。 相机拿爱情的几张图片和临时包精确对准与临时封装的电互连芯片焊盘。 预定的组装位置被沿着输送位于确实传达的第一位置之间的载体，在入口对应于，在所述第二位置，在出口对应。 的模具，约束装置和临时封装在组装预定位置组装并之间的连续性测试那里。 该装置包括：第五此外照相机在晶片处理程序所在的管芯。 该装置具有控制机构，其包括一微处理器和相关联的程序例程并选择性地控制所述机器人臂（i）至夹持器组件移动到盖子喂入器站拿起盖，（ii）向移动夹持器组件地连同盖 拿起由粗相机下面拍摄，（ⅲ）到夹持器组件地连同所述盖和所述模具移动到由细，相机被拍摄的位置，以及（iv）来移动盖子和 预定到沿着输送机位于装配位置。 因此，可以使用用于拆装的方法和装置。

公开(公告)号：EP1411360A3

公开(公告)日：2004-04-28

申请号：EP03029861.6

申请日：1998-02-11

Applicant: MICRON TECHNOLOGY, INC.

Inventor： Hembree, David R. ,  Farnworth, Warren M. ,  Akram, Salman ,  Wood, Alan G. ,  Doherty, C. Patrick ,  Krivy, Andy J.

IPC: G01R1/073 ,  G01R31/316

CPC classification number: G01R1/073 ,  G01R31/2886

Abstract: A probe card (10) for testing semiconductor wafers (12), and a method for testing wafers (12) using the probe card (10) are provided. The probe card (10) includes an interconnect substrate (16) having contact members (20) for establishing electrical communication with contact locations (15) on the wafer (12). The probe card (10) also includes a membrane (18) for physically and electrically connecting the interconnect substrate (16) to the testing apparatus (78), and a compressible member (28) for cushioning the pressure exerted on the interconnect substrate (16) by the testing apparatus (78). An indentation configured to retain bumped contacts (15B) of the wafers is formed in the substrate (16).

Abstract translation: 探针卡（10）用于半导体晶片（12）的测试，半导体晶片（12）具有多个具有多个接触位置的半导体晶片。 晶圆支撑电路朝上，与探头接触。 探针卡包括互连基底（16）和膜（18）。 衬底包括被配置为接触半导体晶片的接触位置的接触构件（20）的图案。 膜将互连基板物理和电连接到安装到测试端口的探针卡夹具（22）。 膜安装板（24）将膜固定到固定装置上。 力施加机构（32）和弹簧加载力施加构件（34）与卡相关联。

公开(公告)号：EP1411359A1

公开(公告)日：2004-04-21

申请号：EP03029860.8

申请日：1998-02-11

Applicant: MICRON TECHNOLOGY, INC.

Inventor： Hembree, David R. ,  Farnworth, Warren M. ,  Akram, Salman ,  Wood, Alan G. ,  Doherty, C. Patrick ,  Krivy, Andy J.

IPC: G01R1/073 ,  G01R31/316

CPC classification number: G01R1/073 ,  G01R31/2886

Abstract: A probe card (10) for testing semiconductor wafers (12), and a method and system (82) for testing wafers (12) using the probe card (10) are provided. The probe card (10) includes an interconnect-substrate (16) having contact members (20) for establishing electrical communication with contact locations (15) on the wafer (12). The probe card (10) also includes a membrane (18) for physically and electrically connecting the interconnect-substrate (16) to the testing apparatus (78), and a compressible member (28) for cushioning the pressure exerted on the interconnect-substrate (16) by the testing apparatus (78).

Abstract translation: 提供了用于测试半导体晶片（12）的探针卡（10）以及用于使用探针卡（10）测试晶片（12）的方法和系统（82）。 探针卡（10）包括具有用于与晶片（12）上的接触位置（15）建立电连接的接触构件（20）的互连衬底（16）。 探针卡（10）还包括用于将互连基板（16）物理地和电气地连接到测试装置（78）的膜（18），以及用于缓冲施加在互连基板上的压力的可压缩构件（28） （16）通过测试装置（78）。

公开(公告)号：EP1691206A2

公开(公告)日：2006-08-16

申请号：EP06075592.3

申请日：1996-04-30

Applicant: MICRON TECHNOLOGY, INC.

Inventor： Wood, Alan G. ,  Farnworth, Warren M. ,  Akram, Salman ,  Hembree, David R.

IPC: G01R31/02 ,  G01R1/073 ,  G01R31/316 ,  G01R1/04 ,  H01L21/66

CPC classification number: G01R1/07314 ,  G01R1/0433 ,  G01R1/0466 ,  G01R1/0483 ,  G01R3/00 ,  G01R31/2863 ,  G01R31/2886 ,  G01R31/2889 ,  G01R31/2893 ,  H01L21/6835 ,  H01L22/20 ,  H01L23/13 ,  H01L23/49816 ,  H01L23/49838 ,  H01L24/48 ,  H01L24/80 ,  H01L24/85 ,  H01L2224/16145 ,  H01L2224/48 ,  H01L2224/85001 ,  H01L2224/85205 ,  H01L2225/06562 ,  H01L2924/00014 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01014 ,  H01L2924/01028 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01039 ,  H01L2924/01042 ,  H01L2924/01074 ,  H01L2924/01077 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/01087 ,  H01L2924/014 ,  H01L2924/09701 ,  H01L2924/14 ,  H01L2924/15151 ,  H01L2924/15174 ,  H01L2924/181 ,  H01L2924/19041 ,  H01L2924/30105 ,  H05K3/0058 ,  H05K3/0067 ,  H05K3/4007 ,  H05K3/423 ,  H05K2201/0133 ,  H05K2201/0347 ,  H05K2201/0367 ,  H05K2201/0394 ,  H05K2201/09481 ,  H05K2201/09563 ,  H05K2203/0307 ,  H05K2203/0723 ,  H01L2224/78 ,  H01L2224/45099 ,  H01L2224/05599 ,  H01L2924/00

Abstract: A method and apparatus for testing unpackaged semiconductor dice includes a mother board (10) and a plurality of interconnects (12) mounted on the mother board (10) and adapted to establish a temporary electrical connection with the dice (14). The interconnects (12) can be formed with a silicon substrate (20) and raised contact members (16) for contacting the bond pads (22) of a die (14). Alternately the interconnects (16) can be formed with micro bump contact members (16) mounted on an insulating film (74). The mother board (10) allows each die (14) to be tested separately for speed and functionality and to also be burn-in tested in parallel using standard burn-in ovens. In an alternate embodiment testing is performed using a mother board/daughter board arrangement. Each daughter board (82) includes interconnects (12) that allow the dice (14) to be tested individually for speed and functionality. Multiple daughter boards (82) can then be mounted to the mother board (10) for burn-in testing using standard burn-in ovens.

Abstract translation: 一种用于测试未封装的半导体裸片的方法和设备包括母板（10）和安装在母板（10）上并且适于与裸片（14）建立暂时电连接的多个互连（12）。 互连件（12）可以形成有硅衬底（20）和凸起的接触构件（16），用于接触管芯（14）的接合焊盘（22）。 或者，可以用安装在绝缘膜（74）上的微凸块接触构件（16）形成互连（16）。 母板（10）允许为了速度和功能而单独测试每个管芯（14），并且还使用标准的老化炉并行地进行老化测试。 在替代实施例中，使用母板/子板布置来执行测试。 每个子板（82）包括互连（12），允许单独测试裸片（14）的速度和功能。 然后可以将多个子板（82）安装到母板（10）上，以使用标准的老化烘箱进行老化测试。

公开(公告)号：EP1411360A2

公开(公告)日：2004-04-21

申请号：EP03029861.6

申请日：1998-02-11

Applicant: MICRON TECHNOLOGY, INC.

Inventor： Hembree, David R. ,  Farnworth, Warren M. ,  Akram, Salman ,  Wood, Alan G. ,  Doherty, C. Patrick ,  Krivy, Andy J.

IPC: G01R1/073 ,  G01R31/316

CPC classification number: G01R1/073 ,  G01R31/2886

Abstract: A probe card (10) for testing semiconductor wafers (12), and a method for testing wafers (12) using the probe card (10) are provided. The probe card (10) includes an interconnect substrate (16) having contact members (20) for establishing electrical communication with contact locations (15) on the wafer (12). The probe card (10) also includes a membrane (18) for physically and electrically connecting the interconnect substrate (16) to the testing apparatus (78), and a compressible member (28) for cushioning the pressure exerted on the interconnect substrate (16) by the testing apparatus (78). An indentation configured to retain bumped contacts (15B) of the wafers is formed in the substrate (16).