公开(公告)号：EP1461862A4

公开(公告)日：2007-12-05

申请号：EP02789818

申请日：2002-11-20

申请人： MICRON TECHNOLOGY INC

发明人： MARTIN CHRIS G

IPC分类号： G11C7/10 ,  G11C11/4093 ,  H03K17/16 ,  G05F1/10 ,  G11C7/00 ,  H02J3/38 ,  H03B1/00

CPC分类号： G11C7/1084 ,  G11C7/1051 ,  G11C7/1057 ,  G11C7/1072 ,  G11C7/1078 ,  G11C11/4093 ,  G11C2207/105 ,  G11C2207/2254

摘要： An active termination circuit (90) is used to set the input impedance of a plurality of input terminals. Each of the input terminals is coupled to a supply voltage through at least one PMOS transistor and to ground through at least one NMOS transistor. The impedances of the transistors are controlled by a control circuit (110) that generates a first control signal to set the impedance of another PMOS transistor (134) to be equal to a first predetermined resistance, and generates a second control signal to set the impedance of another NMOS transistor (144) to be equal to a second predetermined resistance. The first control signal is used to control all of the PMOS transistors and the second control signal is used to control all of the NMOS transistors. As a result, the PMOS and NMOS transistors coupled to each input terminal have impedances corresponding to the first and second resistances, respectively.

公开(公告)号：EP2332143A4

公开(公告)日：2012-03-28

申请号：EP09819740

申请日：2009-10-06

申请人： MICRON TECHNOLOGY INC

发明人： KEETH BRENT ,  MARTIN CHRIS G ,  MANNING TROY A ,  JEDDELOH JOE M ,  COWLES TIMOTHY B ,  REHMEYER JIM ,  LABERGE PAUL A

IPC分类号： G11C8/04 ,  G11C8/06

CPC分类号： G06F12/08 ,  G06F12/10 ,  G11C5/025 ,  G11C29/04 ,  G11C29/18 ,  G11C29/76 ,  G11C29/78 ,  G11C29/808 ,  G11C29/812 ,  G11C29/883 ,  H01L2224/05573 ,  H01L2224/13025 ,  H01L2224/16145 ,  H01L2224/16225 ,  H01L2224/17181 ,  H01L2924/00014 ,  H01L2924/15311 ,  H01L2224/05599

摘要： Various embodiments include apparatus, systems, and methods having multiple dice arranged in a stack in which a defective cell may be replaced by a spare cell on the same die or a different die.