公开(公告)号：EP1379939A4

公开(公告)日：2008-08-20

申请号：EP02707785

申请日：2002-02-15

申请人： MIPS TECH INC

发明人： KISSELL KEVIN D ,  EKNER HARTIG W J ,  STRIBAEK MORTEN ,  JENSEN JAKOB SCHOU

IPC分类号： G06F9/305 ,  G06F7/00 ,  G06F9/30 ,  G06F9/308 ,  G06F7/38

CPC分类号： G06F9/30018 ,  C04B2237/366 ,  G06F7/76 ,  G06F9/30025 ,  G06F9/30032 ,  G06F9/30036

摘要： Partial bitwise permutation instructions are provided in a microprocessor or microcontroller. Partial bitwise permutations may be specified by one or more of the following: a destination specifier, a previous partial value source, a destination subset specifier, and a control specifier. The array unit (3030) within the microprocessor or microcontroller includes two parallel multipliers (Marray 4100 and MParray 4200) and permutation logic (4300). The first array, Marray (4100), performs arithmetic multiplication. Marray (4100) uses Acc1 (3031) Acc2 (3032), M (3033) and sel (3034) as inputs and produces a ResultC and ResultS as outputs. The second array MParray 4200 performs binary polynomial multiplication. Permutation logic (4300) is used to perform various permutations on low order bits of RShold based on the value in RThold (3012).