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115 条记录 (耗时 0.017 秒)

    LINEAR TRANSFORMATION METHOD (VARIANTS)
    1.
    发明公开
    LINEAR TRANSFORMATION METHOD (VARIANTS) 审中-公开

    公开(公告)号：EP3185462A4

    公开(公告)日：2018-08-01

    申请号：EP16833401

    申请日：2016-07-26

    申请人： JOINT STOCK COMPANY INFOTECS

    发明人： BORISENKO NIKOLAY PAVLOVICH ,  URIVSKIY ALEXEY VIKTOROVICH

    IPC分类号： H04L9/06 ,  G06F7/76 ,  G06F9/30

    CPC分类号： H04L9/0631 ,  G06F7/76 ,  G06F9/30101 ,  H04L9/06 ,  H04L2209/12

    摘要： The invention relates to the field of computer engineering and cryptography and, in particular, to methods for implementing linear transformations which operate with a specified speed and require minimum amount of memory, for further usage in devices for cryptographic protection of data. The technical result relates to enabling to select inter-related parameters (performance and required amount of memory) for a particular computing system when implementing a high-dimensional linear transformation. The use of the present method allows to reduce the amount of consumed memory at a given word size of processors employed. To this end, based on a specified linear transformation, a modified linear shift register of Galois-type or Fibonacci-type is generated according to the rules provided in the disclosed method, and the usage thereof enables to obtain the indicated technical result.

    PARTIAL BITWISE PERMUTATIONS
    2.
    发明授权
    PARTIAL BITWISE PERMUTATIONS 有权
    局部BITWISE排列

    公开(公告)号：EP1379939B1

    公开(公告)日：2011-09-21

    申请号：EP02707785.8

    申请日：2002-02-15

    申请人： MIPS Technologies, Inc.

    发明人： KISSELL, Kevin, D. ,  EKNER, Hartig, W., J. ,  STRIBAEK, Morten ,  JENSEN, Jakob Schou

    IPC分类号： G06F7/38 ,  G06F9/30

    CPC分类号： G06F9/30018 ,  C04B2237/366 ,  G06F7/76 ,  G06F9/30025 ,  G06F9/30032 ,  G06F9/30036

    摘要： Partial bitwise permutation instructions are provided in a microprocessor or microcontroller. Partial bitwise permutations may be specified by one or more of the following: a destination specifier, a previous partial value source, a destination subset specifier, and a control specifier. The array unit (3030) within the microprocessor or microcontroller includes two parallel multipliers (Marray 4100 and MParray 4200) and permutation logic (4300). The first array, Marray (4100), performs arithmetic multiplication. Marray (4100) uses Acc1 (3031) Acc2 (3032), M (3033) and sel (3034) as inputs and produces a ResultC and ResultS as outputs. The second array MParray 4200 performs binary polynomial multiplication. Permutation logic (4300) is used to perform various permutations on low order bits of RShold based on the value in RThold (3012).

    DAMPER FOR AUTOMOBILES FOR REDUCING VIBRATION OF AUTOMOBILE BODY
    4.
    发明公开
    DAMPER FOR AUTOMOBILES FOR REDUCING VIBRATION OF AUTOMOBILE BODY 有权
    DÄMPFERFÜRKRAFTFAHRZEUGE ZUR VERRINGERUNG VON SCHWINGUNGEN DER AUTOKAROSSERIE

    公开(公告)号：EP2023007A1

    公开(公告)日：2009-02-11

    申请号：EP07742685.6

    申请日：2007-04-27

    申请人： Shinko Electric Co., Ltd

    发明人： MURAGISHI, Yasushi ,  MORIYA, Hideaki ,  SATO, Yushi ,  FUKUNAGA, Takashi ,  NAKANO, Katsuyoshi ,  NAKAGAWA, Hiroshi ,  FUJII, Takayoshi ,  ONOUE, Takashi ,  NARIHISA, Masaaki

    IPC分类号： F16F15/02 ,  B60G13/16 ,  B60G17/015 ,  B60K5/12 ,  B60R16/02 ,  B62D27/04 ,  G05D19/02 ,  G10K11/178 ,  H04R3/00

    CPC分类号： F16F7/1005 ,  B60G17/018 ,  F16F15/002 ,  G05D19/02 ,  G06F7/76

    摘要： An object of the present invention is to provide a damping apparatus for an automobile, capable of ensuring a high level of reliability while obtaining an excellent damping effect with a simple configuration. The damping apparatus for an automobile that reduces vibrations of an automobile body, includes: an actuator that is attached to the automobile body and drives an auxiliary mass; a current detector that detects a current flowing through an armature of the actuator; a section that detects a terminal voltage applied to the actuator; a calculation circuit that calculates an induced voltage of the actuator, and further calculates at least one of the relative velocity, relative displacement, and relative acceleration of the actuator, based on a current detected by the current detector and the terminal voltage; and a control circuit that drive-controls the actuator based on at least one of the relative velocity, relative displacement, and relative acceleration of the actuator calculated by the calculation circuit.

    摘要翻译： 本发明的目的是提供一种用于汽车的阻尼装置，其能够以简单的构造获得优异的阻尼效果，从而确保高可靠性。 一种减轻汽车车体振动的汽车减震装置，具备：安装在汽车车体上并驱动辅助车体的致动器; 电流检测器，其检测流过致动器的电枢的电流; 检测施加到致动器的端子电压的部分; 计算所述致动器的感应电压的计算电路，并且基于由所述电流检测器检测出的电流和所述端子电压，进一步计算所述致动器的相对速度，相对位移和相对加速度中的至少一个; 以及控制电路，其基于由所述计算电路计算出的所述致动器的相对速度，相对位移和相对加速度中的至少一个来驱动所述致动器。

    PARTIAL BITWISE PERMUTATIONS
    5.
    发明公开
    PARTIAL BITWISE PERMUTATIONS 有权
    局部BITWISE排列

    公开(公告)号：EP1379939A4

    公开(公告)日：2008-08-20

    申请号：EP02707785

    申请日：2002-02-15

    申请人： MIPS TECH INC

    发明人： KISSELL KEVIN D ,  EKNER HARTIG W J ,  STRIBAEK MORTEN ,  JENSEN JAKOB SCHOU

    IPC分类号： G06F9/305 ,  G06F7/00 ,  G06F9/30 ,  G06F9/308 ,  G06F7/38

    CPC分类号： G06F9/30018 ,  C04B2237/366 ,  G06F7/76 ,  G06F9/30025 ,  G06F9/30032 ,  G06F9/30036

    摘要： Partial bitwise permutation instructions are provided in a microprocessor or microcontroller. Partial bitwise permutations may be specified by one or more of the following: a destination specifier, a previous partial value source, a destination subset specifier, and a control specifier. The array unit (3030) within the microprocessor or microcontroller includes two parallel multipliers (Marray 4100 and MParray 4200) and permutation logic (4300). The first array, Marray (4100), performs arithmetic multiplication. Marray (4100) uses Acc1 (3031) Acc2 (3032), M (3033) and sel (3034) as inputs and produces a ResultC and ResultS as outputs. The second array MParray 4200 performs binary polynomial multiplication. Permutation logic (4300) is used to perform various permutations on low order bits of RShold based on the value in RThold (3012).

    Bit-plane extraction operation
    6.
    发明公开
    Bit-plane extraction operation 审中-公开
    位平面提取操作

    公开(公告)号：EP1607858A1

    公开(公告)日：2005-12-21

    申请号：EP04102749.1

    申请日：2004-06-16

    申请人： Koninklijke Philips Electronics N.V.

    发明人： The designation of the inventor has not yet been filed

    IPC分类号： G06F9/308 ,  G06F9/305

    CPC分类号： G06F5/01 ,  G06F5/00 ,  G06F5/015 ,  G06F5/16 ,  G06F7/76 ,  G06F7/762 ,  G06F7/768 ,  G06F9/30018 ,  G06F9/30029 ,  G06F9/30036 ,  H04B1/66 ,  H04B1/667 ,  H04N19/184 ,  H04N19/1883 ,  H04N19/42 ,  H04N19/436

    摘要： A programmable data processing apparatus having a bit-plane extraction operation is described, for extracting data from a value of, for example, 32 bits containing 4 bytes, 1a to 1d. Each byte 1a to 1d comprises 8 bits, (a 0 - a 7 , b 0 - b 7 , c 0 - c 7 and d 0 - d 7 , respectively). The bit-plane extraction operation retrieves one bit from each of these bytes, for example the second bit (a 1 , b 1 , c 1 , d 1 ), which is specified by an argument. The operation involves concatenating these bits (a 1 , b 1 , c 1 , d 1 ) and returning a result value 5. Depending on the particular data processing application, the result value may be bit-reversed to provide a result value 7 (for example, if a bit-reversal is required to deal with endianness, or other reasons). The bit-plane extraction operation can be used as a pre-processing operation in data processing operations such as "sum-of-absolute-differences" in the processing of video data.

    摘要翻译： 描述了一种具有位平面提取操作的可编程数据处理设备，用于从例如包含4个字节1a到1d的32位的值中提取数据。 每个字节1a到1d包括8位，分别是（a0-a7，b0-b7，c0-c7和d0-d7）。 位平面提取操作从每个这些字节中检索一位，例如由参数指定的第二位（a1，b1，c1，d1）。 操作包括连接这些位（a1，b1，c1，d1）并返回结果值5.根据具体的数据处理应用程序，结果值可能会进行位反转以提供结果值7（例如，如果a 需要位反转来处理字节序或其他原因）。 位平面提取操作可​​以用作数据处理操作中的预处理操作，诸如视频数据处理中的“绝对差之和”。

    ARITHMETIC UNIT AND ARITHMETIC METHOD
    8.
    发明公开
    ARITHMETIC UNIT AND ARITHMETIC METHOD 失效
    ARYTHMETISCHE EINHEIT UND ARYMETHISCHES VERFAHREN

    公开(公告)号：EP0930564A4

    公开(公告)日：2002-11-06

    申请号：EP98912729

    申请日：1998-04-08

    申请人： SONY COMPUTER ENTERTAINMENT INC

    发明人： OKA MASAAKI

    IPC分类号： G06F7/57 ,  G06F7/76 ,  G06F9/30 ,  G06F9/302 ,  G06F9/315 ,  G06F9/38 ,  G06F7/00 ,  G06F7/544

    CPC分类号： G06F7/76 ,  G06F7/57 ,  G06F9/30014 ,  G06F9/30025 ,  G06F9/30032 ,  G06F9/30036 ,  G06F9/3885 ,  G06F2207/3828

    摘要： An arithmetic and logic unit (ALU) (330), a shift processing unit (SHT) (340), and a register unit (REG) (350) each of which is divided into, for example, four parts can transfer data to each other through 64-bit buses (BUS) (360, 370, and 380). The data in a plurality of fields in objective words to be inputted to the ALU (330) are exchanged as necessary by means of data exchange units EXC (310) and EXC (320) provided between the buses (360, 370) and the ALU (330). Therefore, the function of arithmetic operation between the plurality of fields in the same word to be processed can be realized in a fewer number of steps than the conventional.

    摘要翻译： 算术和逻辑单元（ALU）（330），移位处理单元（SHT）（340）和寄存器单元（REG）（350）中的每一个被分成例如四个部分，可以向各个 其他通过64位总线（BUS）（360,370和380）。 通过设置在总线（360,370）与ALU（330）之间的数据交换单元EXC（310）和EXC（320），根据需要交换要输入到ALU（330）的客观字中的多个字段中的数据 （330）。 因此，可以以比传统更少的步骤实现要处理的相同字中的多个字段之间的算术运算功能。