公开(公告)号：EP0752722B1

公开(公告)日：2002-10-09

申请号：EP96110587.1

申请日：1996-07-01

申请人： MOTOROLA, INC.

发明人： Ilderem, Vida ,  Kaneshiro, Michael H. ,  Dow, Diann

IPC分类号： H01L29/10 ,  H01L29/36 ,  H01L29/08 ,  H01L21/336

CPC分类号： H01L29/0847 ,  H01L29/1045 ,  H01L29/665 ,  H01L29/6656 ,  H01L29/6659 ,  H01L29/66659

摘要： A low voltage field effect transistor structure (20) is provided with a threshold voltage that is tolerant of process variations that alter the location of a source implant region (41). A first halo region (33) and a second halo region (36) are formed adjacent to source region (41) such that after subsequent thermal processing, a constant doping profile of opposite conductivity as source region (41) is formed in the channel region (23) adjacent the source region (41). The embodiments can be formed either adjacent to only the source region (41) to create a unilateral device, or the doping profile can be formed adjacent to both source region (41) and a drain region (40) to produce a bilateral device. An additional embodiment forms a second implant region in source region (41) to reduce junction leakage and capacitance.

公开(公告)号：EP0676809A3

公开(公告)日：1996-12-11

申请号：EP95104912.1

申请日：1995-04-03

申请人： MOTOROLA, INC.

发明人： Ilderem-Burger, Vida ,  Kaneshiro, Michael H. ,  Dow, Diann ,  Klein, Kevin M. ,  Prendergast, E. James ,  Masqelier, Michael P.

IPC分类号： H01L27/092 ,  H01L29/78

CPC分类号： H01L27/0928 ,  H01L21/823807 ,  H01L29/7835

摘要： Insulated gate field effect transistors (10, 70) having process steps for setting the V T and a device leakage current which are decoupled from the process steps for providing punchthrough protection, thereby lowering a subthreshold swing. In a unilateral transistor (10), a portion (37, 45) of a dopant layer (25, 30) between a source region (48, 51) and a drain region (49, 52) serves as a channel region and sets the V T and the device leakage current. A halo region (34, 39) contains the source region (48, 51) and sets the punchthrough voltage. In a bilateral transistor (70), both a source region (83, 86) and a drain region (84, 87) are contained within halo regions (75, 74, 79, 81). A portion (76, 82) of a dopant layer (25, 30) sets the V T and a leakage current, whereas the halo region (75, 79) sets the punchthrough voltage.

摘要翻译： 绝缘栅场效应晶体管（10,70）具有用于设置VT和器件泄漏电流的工艺步骤，所述工艺步骤与用于提供穿通保护的工艺步骤分离，从而降低亚阈值摆幅。 在单侧晶体管（10）中，源极区域（48,51）和漏极区域（49,52）之间的掺杂剂层（25,30）的部分（37,45）用作沟道区域，并将 VT和器件漏电流。 光晕区域（34,39）包含源极区域（48,51）并设置穿透电压。 在双向晶体管（70）中，源极区域（83,86）和漏极区域（84,87）均包含在光晕区域（75,74,79,81）内。 掺杂剂层（25,30）的一部分（76,82）设定VT和漏电流，而光晕区域（75,79）设定穿透电压。

公开(公告)号：EP0676809A2

公开(公告)日：1995-10-11

申请号：EP95104912.1

申请日：1995-04-03

申请人： MOTOROLA, INC.

发明人： Ilderem-Burger, Vida ,  Kaneshiro, Michael H. ,  Dow, Diann ,  Klein, Kevin M. ,  Prendergast, E. James ,  Masqelier, Michael P.

IPC分类号： H01L27/092 ,  H01L29/78

CPC分类号： H01L27/0928 ,  H01L21/823807 ,  H01L29/7835

摘要： Insulated gate field effect transistors (10, 70) having process steps for setting the V T and a device leakage current which are decoupled from the process steps for providing punchthrough protection, thereby lowering a subthreshold swing. In a unilateral transistor (10), a portion (37, 45) of a dopant layer (25, 30) between a source region (48, 51) and a drain region (49, 52) serves as a channel region and sets the V T and the device leakage current. A halo region (34, 39) contains the source region (48, 51) and sets the punchthrough voltage. In a bilateral transistor (70), both a source region (83, 86) and a drain region (84, 87) are contained within halo regions (75, 74, 79, 81). A portion (76, 82) of a dopant layer (25, 30) sets the V T and a leakage current, whereas the halo region (75, 79) sets the punchthrough voltage.

公开(公告)号：EP0752722A2

公开(公告)日：1997-01-08

申请号：EP96110587.1

申请日：1996-07-01

申请人： MOTOROLA, INC.

发明人： Ilderem, Vida ,  Kaneshiro, Michael H. ,  Dow, Diann

IPC分类号： H01L29/10 ,  H01L29/36

CPC分类号： H01L29/0847 ,  H01L29/1045 ,  H01L29/665 ,  H01L29/6656 ,  H01L29/6659 ,  H01L29/66659

摘要： A low voltage field effect transistor structure (20) is provided with a threshold voltage that is tolerant of process variations that alter the location of a source implant region (41). A first halo region (33) and a second halo region (36) are formed adjacent to source region (41) such that after subsequent thermal processing, a constant doping profile of opposite conductivity as source region (41) is formed in the channel region (23) adjacent the source region (41). The embodiments can be formed either adjacent to only the source region (41) to create a unilateral device, or the doping profile can be formed adjacent to both source region (41) and a drain region (40) to produce a bilateral device. An additional embodiment forms a second implant region in source region (41) to reduce junction leakage and capacitance.

摘要翻译： 低电压场效应晶体管结构（20）被提供有允许改变源植入区域（41）的位置的工艺变化的阈值电压。 形成与源区（41）相邻的第一晕区（33）和第二晕区（36），使得在随后的热处理之后，在通道区域（41）中形成具有相反电导率的恒定掺杂分布 （23）邻近所述源极区域（41）。 这些实施例可以形成为仅与源极区域（41）相邻以产生单边器件，或者可以与源极区域（41）和漏极区域（40）相邻地形成掺杂分布以产生双边器件。 附加实施例在源极区域（41）中形成第二注入区域，以减少结漏电流。

公开(公告)号：EP0676810A3

公开(公告)日：1996-12-11

申请号：EP95104914.7

申请日：1995-04-03

申请人： MOTOROLA, INC.

发明人： Kaneshiro, Michael H. ,  Dow, Diann

IPC分类号： H01L27/092 ,  H01L29/78

CPC分类号： H01L29/66659 ,  H01L21/823807

摘要： Insulated gate field effect transistors (10, 70) having independent process steps for setting lateral and vertical dopant profiles for source and drain regions. In a unilateral transistor (10), portions (48, 50, 51, 55) of the source region are contained within a halo region (34, 41) whereas portions (49, 47, 52, 64) of the drain region are not contained within a halo region. The source region (60, 65) has a first portion (48, 51) for setting a channel length and a second portion (50, 55) for setting a breakdown voltage and a source/drain capacitance. The second portion (50, 55) extends further into the halo region than the first portion (48, 51). In a bilateral transistor (70), portions (84, 89, 80, 91) of the drain region (72, 77) are contained within halo region (75, 79).

公开(公告)号：EP0676810A2

公开(公告)日：1995-10-11

申请号：EP95104914.7

申请日：1995-04-03

申请人： MOTOROLA, INC.

发明人： Kaneshiro, Michael H. ,  Dow, Diann

IPC分类号： H01L27/092 ,  H01L29/78

CPC分类号： H01L29/66659 ,  H01L21/823807

摘要： Insulated gate field effect transistors (10, 70) having independent process steps for setting lateral and vertical dopant profiles for source and drain regions. In a unilateral transistor (10), portions (48, 50, 51, 55) of the source region are contained within a halo region (34, 41) whereas portions (49, 47, 52, 64) of the drain region are not contained within a halo region. The source region (60, 65) has a first portion (48, 51) for setting a channel length and a second portion (50, 55) for setting a breakdown voltage and a source/drain capacitance. The second portion (50, 55) extends further into the halo region than the first portion (48, 51). In a bilateral transistor (70), portions (84, 89, 80, 91) of the drain region (72, 77) are contained within halo region (75, 79).

摘要翻译： IGFET通过（a）提供第一导电类型的半导体衬底，（b）形成具有第一和第二侧的栅极结构，（c）在栅极结构的第一部分和相邻衬底上形成具有开口 在覆盖衬底的区域中的块中，（d）在衬底的与第一侧对准的衬底中形成第一导电类型的第一掺杂区，并且垂直延伸第一距离到衬底中，并横向延伸到第一位置 （e）移除所述注入块并在与所述栅极的第一侧对准的所述第一掺杂区中形成具有第二导电性的第二掺杂区，并垂直延伸第三距离进入所述第一掺杂物，并横向延伸至第 （f）在所述第一掺杂物中形成第二掺杂区域，所述第一掺杂剂垂直延伸第五距离并且与所述第一侧面横向间隔开 （g）在所述栅极的第二侧上的衬底中形成第二类型的第四掺杂区域，其垂直延伸到所述衬底中的第七距离;（h）形成与第三掺杂剂区域接触的第一电极; 第二电极与第四掺杂剂区域接触; 第三电极接触栅极结构。 还要求保护的是具有多于一种栅极结构的方法和其中掺杂区域是卤素区域的方法。