公开(公告)号：EP0718763A1

公开(公告)日：1996-06-26

申请号：EP95118853.1

申请日：1995-11-30

申请人： MOTOROLA, INC.

发明人： Yishay, Oded ,  Jelemensky, Joseph ,  Iles, Alexander L.

IPC分类号： G06F11/00

CPC分类号： G06F11/3656

摘要： A data processor (10) and method which provides show-cycles on a fast multiplexed bus (28) using two distinct modes of operation. A first mode of operation supports a standard show-cycle on a multiplexed bus for interface to a passive device such as a logic analyzer (100). A second mode of operation supports emulation tools (100) with real-time tracking of control functions using a multiplexed bus. During each of the modes of operation of the data processor (10), both read and write show cycles are supported and are consistently provided in a similar format.

摘要翻译： 一种使用两种不同操作模式在快速复用总线（28）上提供显示周期的数据处理器（10）和方法。 第一操作模式支持多路复用总线上的标准显示循环，用于与诸如逻辑分析器（100）的无源设备的接口。 第二种操作模式支持使用多路复用总线实时跟踪控制功能的仿真工具（100）。 在数据处理器（10）的每种操作模式期间，支持读和写显示周期，并以类似的格式一致地提供。

公开(公告)号：EP0712077A1

公开(公告)日：1996-05-15

申请号：EP95116864.0

申请日：1995-10-26

申请人： MOTOROLA, INC.

发明人： Iles, Alexander L. ,  Jelemensky, Joseph ,  Yishay, Oded

IPC分类号： G06F11/00

CPC分类号： G06F11/3632 ,  G06F11/3648

摘要： An integrated circuit terminal of a data processing system (10) is used to communicate multiplexed signals with an external device. During a reset operation in which a reset signal is asserted, a desired internal clock signal is driven to the integrated circuit terminal such that an emulation system (52) may use the internal clock signal to synchronize an emulation operation. After the reset signal is negated, the emulation system synthesizes the internal clock signal for use during emulation. External visibility of a write operation to a register which controls pertinent signal parameters is provided via other integrated circuit terminals when the data processor operates in an emulation mode. The external visibility allows the development system to make similar changes to corresponding signal parameters therein. Therefore, the development system is able to accurately synchronize an emulation operation even when signal parameters are modified during operation.

摘要翻译： 数据处理系统（10）的集成电路终端用于与外部设备通信多路复用信号。 在其中确定复位信号的复位操作期间，期望的内部时钟信号被驱动到集成电路端子，使得仿真系统（52）可以使用内部时钟信号来同步仿真操作。 在复位信号被否定之后，仿真系统合成内部时钟信号，以便在仿真期间使用。 当数据处理器以仿真模式运行时，通过其他集成电路终端提供对控制相关信号参数的寄存器的写入操作的外部可视性。 外部可视性允许开发系统对其中的相应信号参数进行类似的改变。 因此，即使在操作期间修改信号参数时，开发系统也能够精确地同步仿真操作。

公开(公告)号：EP0702297B1

公开(公告)日：2000-10-11

申请号：EP95112227.4

申请日：1995-08-03

申请人： MOTOROLA, INC.

发明人： Yishay, Oded ,  Jelemensky, Joseph

IPC分类号： G06F11/00

CPC分类号： G06F11/3648

公开(公告)号：EP0702297A1

公开(公告)日：1996-03-20

申请号：EP95112227.4

申请日：1995-08-03

申请人： MOTOROLA, INC.

发明人： Yishay, Oded ,  Jelemensky, Joseph

IPC分类号： G06F11/00

CPC分类号： G06F11/3648

摘要： Existing chip select comparator logic (42) is used to compare a portion of the address value with a range of chip select addresses to provide match signals for use by both the chip select logic (70) and a breakpoint logic circuit (50.x). The match signal is used by the chip select logic circuit (70) and is reused by the breakpoint logic circuit to perform a different and distinct function. By using the match signal and a breakpoint enable bit, the breakpoint logic circuit selectively asserts a breakpoint signal. Subsequently, a central processing unit (12) receives the breakpoint signal and initiates a breakpoint exception operation to determine whether the breakpoint condition is met and whether further action should be taken.

摘要翻译： 现有的芯片选择比较器逻辑（42）用于将地址值的一部分与芯片选择地址的范围进行比较，以提供芯片选择逻辑（70）和断点逻辑电路（50x）两者使用的匹配信号， 。 匹配信号由芯片选择逻辑电路（70）使用，并被断点逻辑电路重用以执行不同且不同的功能。 通过使用匹配信号和断点使能位，断点逻辑电路选择性地断言断点信号。 随后，中央处理单元（12）接收断点信号并启动断点异常操作，以确定是否满足断点条件以及是否应采取进一步措施。

公开(公告)号：EP0694828A3

公开(公告)日：1996-04-03

申请号：EP95111400.8

申请日：1995-07-20

申请人： MOTOROLA, INC.

发明人： Yishay, Oded ,  LaViolette, William P. ,  Pechonis, Daniel W.

IPC分类号： G06F1/00

CPC分类号： G06F12/1466 ,  G11C7/24 ,  G11C8/20

摘要： A data processing system (10) allows an authorized user to unlock a security mode by providing a code stored in a plurality of mask registers (60,62,66) such that the system is selectively allowed to communicate with an external device. When an reset signal is received, a selector (48) selects a first mask register (60) and retrieves a first stored address value and a first stored data value therefrom. The first stored address and data values are respectively compared with a first address value and a first data value by a comparator (44). This process of selecting and comparing continues until a final match signal is asserted. When the final match signal is asserted, a secure signal is negated and the system may communicate with the external user.

公开(公告)号：EP0694828A2

公开(公告)日：1996-01-31

申请号：EP95111400.8

申请日：1995-07-20

申请人： MOTOROLA, INC.

发明人： Yishay, Oded ,  LaViolette, William P. ,  Pechonis, Daniel W.

IPC分类号： G06F1/00

CPC分类号： G06F12/1466 ,  G11C7/24 ,  G11C8/20

摘要： A data processing system (10) allows an authorized user to unlock a security mode by providing a code stored in a plurality of mask registers (60,62,66) such that the system is selectively allowed to communicate with an external device. When an reset signal is received, a selector (48) selects a first mask register (60) and retrieves a first stored address value and a first stored data value therefrom. The first stored address and data values are respectively compared with a first address value and a first data value by a comparator (44). This process of selecting and comparing continues until a final match signal is asserted. When the final match signal is asserted, a secure signal is negated and the system may communicate with the external user.

摘要翻译： 数据处理系统（10）允许授权用户通过提供存储在多个屏蔽寄存器（60,62,66）中的代码来解锁安全模式，使得系统被选择性地允许与外部设备通信。 当接收到复位信号时，选择器（48）选择第一屏蔽寄存器（60）并且从中检索第一存储的地址值和第一存储的数据值。 第一存储的地址和数据值分别通过比较器（44）与第一地址值和第一数据值进行比较。 该选择和比较的过程继续进行直到最终匹配信号被断言。 当最终匹配信号被断言时，安全信号被否定，并且系统可以与外部用户通信。 $$