公开(公告)号：EP4414850A1

公开(公告)日：2024-08-14

申请号：EP24156846.8

申请日：2024-02-09

申请人： NXP USA, Inc.

发明人： Miller, Gary L. ,  Singh, Devendra Bahadur ,  Gamoneda, Jonathan ,  Kimelman, Paul ,  Yishay, Oded

IPC分类号： G06F11/36 ,  G01R31/317 ,  G06F11/22

CPC分类号： G06F11/3656 ,  G06F11/2242 ,  G01R31/31705 ,  G06F11/362

摘要： Systems and methods for debugging multi-core processors with configurable isolated partitions have been described. In an illustrative, non-limiting embodiment, an integrated circuit, may include: a plurality of Cross-Trigger Matrices (CTMs) configured to establish a debug network among a plurality of muti-cluster tiles (MCTs), where each MCT includes a plurality of processor cores, and where each processor core is assigned to a respective isolated partition of processor cores; and a System Interface (SI) coupled to the plurality of CTMs, where the SI is configured to control the plurality of CTMs to enable or disable at least a portion of the debug network to allow an isolated partition to be debugged independently of another isolated partition. A method may include enabling or disabling, by the SI, buses between the MCTs to create isolated debug networks, each isolated debug network corresponding to a distinct isolated partition of processor cores.

公开(公告)号：EP3352083A1

公开(公告)日：2018-07-25

申请号：EP16848168.7

申请日：2016-09-24

申请人： Huawei Technologies Co., Ltd.

发明人： WANG, Mingfa ,  YU, Gang ,  WANG, Haichuan

IPC分类号： G06F11/36

CPC分类号： G06F11/362 ,  G06F9/445 ,  G06F9/48 ,  G06F11/36 ,  G06F11/3656

摘要： Embodiments of the present invention relate to the field of computer technologies. The embodiments of the present invention provide a debugging method, including: stopping running, by a core A of the multi-core processor after completing execution of a processing routine of a preset event, and sending a running stop signal to other cores in a process of stopping running; after receiving a first stop termination instruction and resuming running, executing, by the core A, a debugging information collection function to collect debugging information of the preset event, and stopping running after completing the execution of the debugging information collection function; after receiving a second stop termination instruction and resuming running, sending, by the core A, a running resumption instruction to the other cores; and knocking, by the core A, the pending breakpoint in a process of running an operation object of the preset event, so as to enter a debugging state. According to the technical solutions provided in the embodiments of the present invention, kernel mode code and user mode code can be debugged on a same debugging platform. In addition, the embodiments of the present invention further provide a corresponding debugging apparatus.

公开(公告)号：EP3350691A1

公开(公告)日：2018-07-25

申请号：EP16778919.7

申请日：2016-09-13

申请人： Microsoft Technology Licensing, LLC

发明人： BURGER, Douglas C. ,  SMITH, Aaron L.

IPC分类号： G06F9/38 ,  G06F12/0862 ,  G06F9/30

CPC分类号： G06F9/3016 ,  G06F9/268 ,  G06F9/30007 ,  G06F9/30021 ,  G06F9/30036 ,  G06F9/3004 ,  G06F9/30043 ,  G06F9/30047 ,  G06F9/3005 ,  G06F9/30058 ,  G06F9/30072 ,  G06F9/30076 ,  G06F9/30087 ,  G06F9/3009 ,  G06F9/30098 ,  G06F9/30101 ,  G06F9/30105 ,  G06F9/3013 ,  G06F9/30145 ,  G06F9/30167 ,  G06F9/30189 ,  G06F9/32 ,  G06F9/321 ,  G06F9/345 ,  G06F9/35 ,  G06F9/355 ,  G06F9/3557 ,  G06F9/3802 ,  G06F9/3804 ,  G06F9/3822 ,  G06F9/3824 ,  G06F9/383 ,  G06F9/3836 ,  G06F9/3838 ,  G06F9/3842 ,  G06F9/3848 ,  G06F9/3851 ,  G06F9/3853 ,  G06F9/3855 ,  G06F9/3859 ,  G06F9/3867 ,  G06F9/3891 ,  G06F9/466 ,  G06F9/528 ,  G06F11/36 ,  G06F11/3648 ,  G06F11/3656 ,  G06F12/0806 ,  G06F12/0811 ,  G06F12/0862 ,  G06F12/0875 ,  G06F12/1009 ,  G06F13/4221 ,  G06F15/7867 ,  G06F15/80 ,  G06F15/8007 ,  G06F2212/452 ,  G06F2212/602 ,  G06F2212/604 ,  G06F2212/62 ,  Y02D10/13 ,  Y02D10/14 ,  Y02D10/151

摘要： Apparatus and methods are disclosed for nullifying memory store instructions and one or more registers identified in a target field of a nullification instruction. In some examples of the disclosed technology, an apparatus can include memory and one or more block-based processor cores configured to fetch and execute a plurality of instruction blocks. One of the cores can include a control unit configured, based at least in part on receiving a nullification instruction, to obtain an instruction identification for a memory access instruction of a plurality of memory access instructions and a register identification of at least one of a plurality of registers, based on a first and second target fields of the nullification instruction. The at least one register and the memory access instruction associated with the instruction identification are nullified. Based on the nullified memory access instruction, a subsequent memory access instruction is executed.

公开(公告)号：EP3200557A4

公开(公告)日：2018-04-25

申请号：EP15844437

申请日：2015-07-23

申请人： SHARP KK

发明人： UEMURA KATSUNARI ,  YAMADA SHOHEI ,  TSUBOI HIDEKAZU

IPC分类号： H04W72/04 ,  H04W76/14 ,  H04W92/18

CPC分类号： G01R31/31903 ,  G06F11/3656 ,  H04B7/061 ,  H04L12/5692 ,  H04M9/027 ,  H04W24/00 ,  H04W28/06 ,  H04W72/02 ,  H04W72/042 ,  H04W76/14 ,  H04W92/18

摘要： Provided is a technique related to a terminal apparatus, a base station apparatus, a communication system, a communication method, and an integrated circuit that are capable of efficiently performing device-to-device communication. In a case where a terminal apparatus capable of direct communication between terminal apparatuses starts a timer corresponding to a group index that identifies short-range group communication, to which the terminal apparatus belongs, and the timer expires, switching is performed from a first radio resource allocation method, by which a radio resource to be used for the direct communication is requested to a base station apparatus, to a second radio resource allocation method by which the terminal apparatus selects a radio resource to be used for the direct communication.

公开(公告)号：EP2391969B1

公开(公告)日：2017-08-02

申请号：EP10736189.1

申请日：2010-01-13

申请人： NXP USA, Inc.

发明人： CASE, Lawrence L. ,  ASHKENAZI, Asaf ,  CHHABRA, Ruchir ,  COVEY, Carlin R. ,  HARTLEY, David H. ,  MACKIE, Troy E. ,  MUIR, Alistair N. ,  REDMAN, Mark D. ,  TKACIK, Thomas E. ,  VAGLICA, John J. ,  ZIOLKOWSKI, Rodney D.

IPC分类号： G06F11/36 ,  H04L9/32

CPC分类号： G06F11/3656 ,  H04L9/3247 ,  H04L9/3271

公开(公告)号：EP2684062B1

公开(公告)日：2016-05-04

申请号：EP11860143.4

申请日：2011-12-21

申请人： Intel Corporation

发明人： PATIL, Srinivas ,  JAS, Abhijit

IPC分类号： G01R31/28 ,  G06F11/22 ,  G06F11/36 ,  G06F11/263

CPC分类号： G06F11/263 ,  G06F11/2242 ,  G06F11/3656

公开(公告)号：EP2684062A2

公开(公告)日：2014-01-15

申请号：EP11860143.4

申请日：2011-12-21

申请人： Intel Corporation

发明人： PATIL, Srinivas ,  JAS, Abhijit

IPC分类号： G01R31/28 ,  G06F1/00 ,  G06F13/14

CPC分类号： G06F11/263 ,  G06F11/2242 ,  G06F11/3656

摘要： A Test Access Mechanism (TAM) architecture for facilitating testing of IP blocks integrated on a System on a Chip (SoC). The TAM architecture includes a Test Controller and one or more Test Wrappers that are integrated on the SoC proximate to IP blocks. Test data and commands corresponding to input from an external tester are packaged by the Test Controller and sent to the Test Wrappers via an interconnect fabric. The Test Wrappers employ one or more test ports to provide test data, control, and/or stimulus signals to the IP block to facilitate circuit-level testing of the IP block. Test results for the circuit-level tests are returned to the Test Controller via the fabric. Test Wrappers may be configured to pass through interconnect signals, enabling functional testing of IP blocks to be facilitated via test packages and test results transmitted between the Test Controller and the IP blocks via the fabric.

公开(公告)号：EP2062141A2

公开(公告)日：2009-05-27

申请号：EP07826352.2

申请日：2007-09-12

申请人： Nokia Corporation

发明人： PIRTTIMÄKI, Antti ,  MERILAHTI, Miikka ,  KÜHNIS, Rolf ,  HIETAMÄKI, Jouni

IPC分类号： G06F11/36

CPC分类号： G06F11/3656 ,  G06F11/2733

摘要： This invention relates to a method, an apparatus, an electronic device, a system, and a computer program product for selecting at least one component out of at least one maintenance component and at least one non-maintenance component, wherein said at least one maintenance component and said at least one non-maintenance component represent electronic components arranged in an apparatus; and switching an external connector of said apparatus to said at least one selected component.

公开(公告)号：EP1475715A3

公开(公告)日：2009-02-25

申请号：EP04252332.4

申请日：2004-04-21

申请人： STMicroelectronics, Inc.

发明人： Tamagno, David ,  Tournemille, Jerome

IPC分类号： G06F11/36

CPC分类号： G06F11/3656

摘要： The present invention is a smart card device that can be debugged and software developed using at least one interrupt endpoint without adding an additional port. At least one memory stores a debug monitor program and instructions for completing smart card transactions. An interface is defined by a plurality of communication pipes and respective endpoints, including at least one interrupt endpoint. A microprocessor is operatively connected to the interface and memory and configures the interrupt endpoint as a debug port for debugging and software development using the debug monitor program.

公开(公告)号：EP2002341A2

公开(公告)日：2008-12-17

申请号：EP07758179.1

申请日：2007-03-08

申请人： Qualcomm Incorporated

发明人： SEVERSON, Matthew Levi ,  BURKE, Joseph Patrick ,  POTTIER, Philip

IPC分类号： G06F11/36

CPC分类号： G06F11/3656

摘要： A method of performing a debug operation on a processor after a power collapse is provided. An idle state of the processor is detected during an execution mode of the processor. The idle state is determined to be associated with a power collapse event. A debug state of the processor is restored by loading debug registers within the processor during the execution mode.