公开(公告)号：EP1457993A3

公开(公告)日：2005-07-27

申请号：EP04006012.1

申请日：2004-03-12

申请人： Marvell World Trade Ltd.

发明人： Lee, Winston ,  Sutardja, Sehat ,  Pannell, Donald

IPC分类号： G11C7/10 ,  H04L12/56

CPC分类号： G11C7/1075

摘要： A multiport memory architecture, systems including the same and methods for using the same. The architecture generally includes (a) a memory array; (b) a plurality of ports configured to receive and/or transmit data; and (c) a plurality of port buffers, each of which is configured to transmit the data to and/or receive the data from one or more of the ports, and all of which are configured to (i) transmit the data to the memory array on a first common bus and (ii) receive the data from the memory array on a second common bus. The systems generally include those that embody one or more of the inventive concepts disclosed herein. The methods generally relate to writing blocks of data to, reading blocks of data from, and/or transferring blocks of data across a memory. The present invention advantageously reduces latency in data communications, particularly in network switches, by tightly coupling port buffers to the main memory and advantageously using point-to-point communications over long segments of the memory read and write paths, thereby reducing routing congestion and enabling the elimination of a FIFO. The invention advantageously shrinks chip size and provides increased data transmission rates and throughput, and in preferred embodiments, reduced resistance and/or capacitance in the memory read and write busses.

公开(公告)号：EP1457993B1

公开(公告)日：2010-09-08

申请号：EP04006012.1

申请日：2004-03-12

申请人： Marvell World Trade Ltd.

发明人： Lee, Winston ,  Sutardja, Sehat ,  Pannell, Donald

IPC分类号： G11C7/10 ,  H04L12/56

CPC分类号： G11C7/1075

公开(公告)号：EP1457993A2

公开(公告)日：2004-09-15

申请号：EP04006012.1

申请日：2004-03-12

申请人： Marvell World Trade Ltd.

发明人： Lee, Winston ,  Sutardja, Sehat ,  Pannell, Donald

IPC分类号： G11C7/10

CPC分类号： G11C7/1075

摘要： A multiport memory architecture, systems including the same and methods for using the same. The architecture generally includes (a) a memory array; (b) a plurality of ports configured to receive and/or transmit data; and (c) a plurality of port buffers, each of which is configured to transmit the data to and/or receive the data from one or more of the ports, and all of which are configured to (i) transmit the data to the memory array on a first common bus and (ii) receive the data from the memory array on a second common bus. The systems generally include those that embody one or more of the inventive concepts disclosed herein. The methods generally relate to writing blocks of data to, reading blocks of data from, and/or transferring blocks of data across a memory. The present invention advantageously reduces latency in data communications, particularly in network switches, by tightly coupling port buffers to the main memory and advantageously using point-to-point communications over long segments of the memory read and write paths, thereby reducing routing congestion and enabling the elimination of a FIFO. The invention advantageously shrinks chip size and provides increased data transmission rates and throughput, and in preferred embodiments, reduced resistance and/or capacitance in the memory read and write busses.

摘要翻译： 一种多端口存储器体系结构，系统，包括用于使用相同的相同和方法。 该体系结构基因集会包括（a）一个存储器阵列; （B）配置成接收和/或发送数据端口的一个多元化; 和（c）端口缓冲器的复数，每个的所有其被配置为将数据传输到和/或从一个或多个端口接收的数据，并且所有这些都被配置为（i）所述数据传输到存储器 第一公共总线上阵列和（ii）接收第二公共总线上从存储器阵列中的数据。 该系统基因集会包括thosethat体现的一个或多个游离缺失在本发明构思的光盘。 方法基因反弹涉及写入数据的块，从读出的数据的块，和/或跨越存储器的数据传递环块。 本发明有利地降低等待时间的数据通信，特别是在网络交换机，通过端口缓冲器紧密耦合到主存储器，并且有利地使用点对点通信在读取存储器的长段和写入路径，从而减少路由拥塞和使 消除一个FIFO的。 本发明有利地缩小芯片尺寸和提供增加的数据传输速率和吞吐量，并且在优选的实施例中，减小的电阻和/或电容中读出的存储器和写总线。