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    APPARATUS FOR COMMUNICATING ANOTHER DEVICE
    3.
    发明授权
    APPARATUS FOR COMMUNICATING ANOTHER DEVICE 有权
    用于传送其他设备的设备

    公开(公告)号：EP3171533B1

    公开(公告)日：2018-03-07

    申请号：EP17150059.8

    申请日：2012-01-20

    申请人： MediaTek Inc.

    发明人： LIOU, Ming-Luen ,  CHIOU, Rong-Liang

    IPC分类号： H04B15/02

    CPC分类号： G06F1/04 ,  G06F1/06 ,  G06F13/4086 ,  H03K17/16 ,  H03K19/00346 ,  H04B15/02

    摘要： The present invention relates to a semiconductor chip which is capable of mounting on a printed circuit board. The semiconductor chip comprises: a signal generating module (211, 213; 212, 214, 216) for generating a first signal and a second signal; a first output node (251; 253) for transmitting the first signal; and a second output node (252; 219; 301) for transmitting the second signal, wherein the phase of the second signal is opposite to that of the first signal; wherein the second output node (219, 252, 301, 403, 407) is utilized for connecting a terminator device (205, 209) mounted on the printed circuit board.

    APPARATUS FOR COMMUNICATING ANOTHER DEVICE
    4.
    发明公开
    APPARATUS FOR COMMUNICATING ANOTHER DEVICE 有权
    用于传送其他设备的设备

    公开(公告)号：EP3171533A1

    公开(公告)日：2017-05-24

    申请号：EP17150059.8

    申请日：2012-01-20

    申请人： MediaTek Inc.

    发明人： LIOU, Ming-Luen ,  CHIOU, Rong-Liang

    IPC分类号： H04B15/02

    CPC分类号： G06F1/04 ,  G06F1/06 ,  G06F13/4086 ,  H03K17/16 ,  H03K19/00346 ,  H04B15/02

    摘要： The present invention relates to a semiconductor chip which is capable of mounting on a printed circuit board. The semiconductor chip comprises: an internal clock circuit for generating an internal clock signal (ICLK); a first phase shift device (214) for shifting the phase of an external clock signal (OCLK) and outputting a phase shifting clock signal (PCLK); a multiplexer (216), coupled to the internal clock circuit and the first phase shift device, for selectively outputting one of the internal clock signal and the phase shifting clock signal to be a first clock signal; a second phase shift device (229), coupled to the multiplexer, for shifting the phase of the first clock signal and outputting a second clock signal; an first output pad (253), coupled to the multiplexer for outputting the first clock signal; and a controllable pad (301), coupled to the first phase shift device and the second phase shift device; wherein the controllable pad is controlled to selectively act as an input pad for receiving the external clock signal and transmitting the external clock signal to the first phase shift device, or act as a second output pad for transmitting the second clock signal.

    摘要翻译： 本发明涉及一种能够安装在印刷电路板上的半导体芯片。 该半导体芯片包括：用于产生内部时钟信号（ICLK）的内部时钟电路; 第一相移装置（214），用于移动外部时钟信号（OCLK）的相位并输出相移时钟信号（PCLK）; 耦接于该内部时钟电路与该第一相移装置，用以选择性地输出该内部时钟信号与该相移时钟信号其中之一为一第一时钟信号; 耦合到所述多路复用器的第二相移装置（229），用于移位所述第一时钟信号的相位并输出第二时钟信号; 一第一输出垫（253），耦接于该多工器，用以输出该第一时钟信号; 和耦合到第一相移装置和第二相移装置的可控制垫（301） 其中所述可控制焊盘被控制为选择性地充当用于接收所述外部时钟信号并将所述外部时钟信号传输到所述第一相移装置的输入焊盘或充当用于传输所述第二时钟信号的第二输出焊盘。

    PACKET PROCESSING APPARATUS AND METHOD CAPABLE OF GENERATING MODIFIED PACKETS BY MODIFYING PAYLOADS OF SPECIFIC PACKETS IDENTIFIED FROM RECEIVED PACKETS
    6.
    发明公开
    PACKET PROCESSING APPARATUS AND METHOD CAPABLE OF GENERATING MODIFIED PACKETS BY MODIFYING PAYLOADS OF SPECIFIC PACKETS IDENTIFIED FROM RECEIVED PACKETS 有权
    分组处理设备和能够通过修改从接收到的分组中识别出的特定分组的载荷来产生经修改的分组的方法

    公开(公告)号：EP2361474A1

    公开(公告)日：2011-08-31

    申请号：EP09834084.7

    申请日：2009-12-21

    申请人： Mediatek Inc.

    发明人： YEH, Chin-Wang ,  YEH, You-Min ,  CHIOU, Rong-Liang ,  DENG, Yu-Hsiung ,  WANG, Ching-Chieh

    IPC分类号： H04L29/06

    CPC分类号： H04N21/2389 ,  H04N21/23608 ,  H04N21/2362 ,  H04N21/426 ,  H04N21/434 ,  H04N21/4385

    摘要： A packet processing apparatus includes a packet identifying unit and a packet modifying unit. The packet identifying unit is utilized for receiving a plurality of packets and checking identification information derived from the received packets to identify first packets from the received packets. The packet modifying unit is coupled to the packet identifying unit, and is utilized for checking payloads of the first packets to identify second packets from the first packets, where each of the second packets has specific data included in a payload thereof, and for modifying at least the payload of each of the second packets.

    摘要翻译： 分组处理设备包括分组识别单元和分组修改单元。 分组识别单元用于接收多个分组并且检查从所接收的分组导出的识别信息以从所接收的分组中识别第一分组。 分组修改单元耦合到分组识别单元，并用于检查第一分组的有效载荷以识别来自第一分组的第二分组，其中每个第二分组具有包含在其有效载荷中的特定数据，并用于在 至少每个第二分组的有效载荷。