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    DYNAMIC FRAME RATE ADJUSTMENT MECHANISM
    2.
    发明公开
    DYNAMIC FRAME RATE ADJUSTMENT MECHANISM 审中-公开

    公开(公告)号：EP3869493A1

    公开(公告)日：2021-08-25

    申请号：EP21156370.5

    申请日：2021-02-10

    申请人： MediaTek Inc.

    发明人： FAN, Kang-Yi ,  LIANG, Chin-Wen ,  LIU, Chang-Chu ,  CHANG, Sheng-Hsiang ,  YEH, You-Min

    IPC分类号： G09G5/00 ,  G11B27/031

    摘要： A control method of a processor is provided, wherein the control method comprises the steps of: transmitting image data of a first frame to an integrated circuit, wherein the first frame corresponds to a first frame rate; determining a second frame rate of a second frame next to the first frame; determining if a difference between the second frame rate and the first frame rate belongs to a large scale frame rate adjustment or a small scale frame rate adjustment; if the difference between the second frame rate and the first frame rate belongs to the large scale frame rate adjustment, using a first mode to transmit image data of the second frame; and if the difference between the second frame rate and the first frame rate belongs to the small scale frame rate adjustment, using a second mode to transmit image data of the second frame.

    DYNAMIC FRAME RATE MECHANISM FOR DISPLAY DEVICE
    3.
    发明公开
    DYNAMIC FRAME RATE MECHANISM FOR DISPLAY DEVICE 审中-公开

    公开(公告)号：EP3876222A1

    公开(公告)日：2021-09-08

    申请号：EP21159416.3

    申请日：2021-02-25

    申请人： MEDIATEK INC.

    发明人： LIU, Chang-Chu ,  CHANG, Sheng-Hsiang ,  FAN, Kang-Yi ,  YEH, You-Min

    IPC分类号： G09G3/20 ,  G09G5/00 ,  G09G5/12

    摘要： The present invention provides a processor including a source generator, a request synchronization signal generator and an output circuit. The source generator is configured to generate image data of a frame. The request synchronization signal generator is configured to generate a request synchronization signal to an integrated circuit only after the source generator generates the image data of the frame completely, wherein the request synchronization signal is used to trigger the integrated circuit to send a synchronization signal to the processor. The output circuit is configured to send the image data of the frame to the integrated circuit only after receiving the synchronization signal generated from the integrated circuit in response to the request synchronization signal.

    PACKET PROCESSING APPARATUS AND METHOD CAPABLE OF GENERATING MODIFIED PACKETS BY MODIFYING PAYLOADS OF SPECIFIC PACKETS IDENTIFIED FROM RECEIVED PACKETS
    6.
    发明公开
    PACKET PROCESSING APPARATUS AND METHOD CAPABLE OF GENERATING MODIFIED PACKETS BY MODIFYING PAYLOADS OF SPECIFIC PACKETS IDENTIFIED FROM RECEIVED PACKETS 有权
    分组处理设备和能够通过修改从接收到的分组中识别出的特定分组的载荷来产生经修改的分组的方法

    公开(公告)号：EP2361474A1

    公开(公告)日：2011-08-31

    申请号：EP09834084.7

    申请日：2009-12-21

    申请人： Mediatek Inc.

    发明人： YEH, Chin-Wang ,  YEH, You-Min ,  CHIOU, Rong-Liang ,  DENG, Yu-Hsiung ,  WANG, Ching-Chieh

    IPC分类号： H04L29/06

    CPC分类号： H04N21/2389 ,  H04N21/23608 ,  H04N21/2362 ,  H04N21/426 ,  H04N21/434 ,  H04N21/4385

    摘要： A packet processing apparatus includes a packet identifying unit and a packet modifying unit. The packet identifying unit is utilized for receiving a plurality of packets and checking identification information derived from the received packets to identify first packets from the received packets. The packet modifying unit is coupled to the packet identifying unit, and is utilized for checking payloads of the first packets to identify second packets from the first packets, where each of the second packets has specific data included in a payload thereof, and for modifying at least the payload of each of the second packets.

    摘要翻译： 分组处理设备包括分组识别单元和分组修改单元。 分组识别单元用于接收多个分组并且检查从所接收的分组导出的识别信息以从所接收的分组中识别第一分组。 分组修改单元耦合到分组识别单元，并用于检查第一分组的有效载荷以识别来自第一分组的第二分组，其中每个第二分组具有包含在其有效载荷中的特定数据，并用于在 至少每个第二分组的有效载荷。