公开(公告)号：EP1110238B1

公开(公告)日：2009-01-07

申请号：EP98938028.2

申请日：1998-07-23

申请人： Micron Technology, Inc.

发明人： KO, Kei-Yu

IPC分类号： H01L21/311

CPC分类号： H01L21/31116

摘要： Disclosed is a process for removing doped silicon dioxide from a structure selectively to undoped silicon dioxide. A structure having both doped and undoped silicon dioxide regions is exposed to a high density plasma etch having a fluorinated etch chemistry. Doped silicon dioxide is preferably removed thereby at a rate 10 times or more greater than that of undoped silicon dioxide. The etch is conducted in a chamber having an upper electrode to which a source power is applied and a lower electrode to which a bias power is applied sufficient to generate a power density on a surface of the structure such that the source power density is in a range less than or equal to about 1000 W per 200-mm diameter wafer surface. The high density plasma etch has an ion density not less than about 10 ions/cm . A variety of structures are formed with the etch process, including self-aligned contacts to a semiconductor substrate.

公开(公告)号：EP1110238A1

公开(公告)日：2001-06-27

申请号：EP98938028.2

申请日：1998-07-23

申请人： MICRON TECHNOLOGY, INC.

发明人： KO, Kei-Yu

IPC分类号： H01L21/311

CPC分类号： H01L21/31116

摘要： Disclosed is a process for removing doped silicon dioxide from a structure selectively to undoped silicon dioxide. A structure having both doped and undoped silicon dioxide regions is exposed to a high density plasma etch having a fluorinated etch chemistry. Doped silicon dioxide is preferably removed thereby at a rate 10 times or more greater than that of undoped silicon dioxide. The etch is conducted in a chamber having an upper electrode to which a source power is applied and a lower electrode to which a bias power is applied sufficient to generate a power density on a surface of the structure such that the source power density is in a range less than or equal to about 1000 W per 200-mm diameter wafer surface. The high density plasma etch has an ion density not less than about 109 ions/cm3. A variety of structures are formed with the etch process, including self-aligned contacts to a semiconductor substrate.

公开(公告)号：EP1297564B1

公开(公告)日：2008-09-17

申请号：EP01956164.6

申请日：2001-07-05

申请人： Micron Technology, Inc.

发明人： KO, Kei-Yu ,  LI, Li ,  BLALOCK, Guy, T.

IPC分类号： H01L21/311

CPC分类号： H01L21/76897 ,  H01L21/31116 ,  H01L21/76802

摘要： An etchant including C2HxFy, where x is an integer from two to five, inclusive, where y is an integer from one to four, inclusive, and where x plus y equals six. The etchant etches doped silicon dioxide with selectivity over both undoped silicon dioxide and silicon nitride. Thus, undoped silicon dioxide and silicon nitride may be employed as etch stops in dry etch processes which utilize the C2HxFy-containing etchant. C2HxFy may be employed as either a primary etchant or as an additive to another etchant or etchant mixture. Semiconductor devices (10) that include structures that have been patterned with an etchant of the present invention or in accordance with the method of the present invention are also disclosed. Specifically, the present invention includes semiconductor devices (10) including doped silicon oxide structures (24) with substantially vertical sidewalls (34) and adjacent undoped silicon oxide or silicon nitride structures (36) exposed adjacent the sidewall (34).

公开(公告)号：EP1297564A2

公开(公告)日：2003-04-02

申请号：EP01956164.6

申请日：2001-07-05

申请人： Micron Technology, Inc.

发明人： KO, Kei-Yu ,  LI, Li ,  BLALOCK, Guy, T.

IPC分类号： H01L21/311

CPC分类号： H01L21/76897 ,  H01L21/31116 ,  H01L21/76802

摘要： An etchant including C2HxFy, where x is an integer from two to five, inclusive, where y is an integer from one to four, inclusive, and where x plus y equals six. The etchant etches doped silicon dioxide with selectivity over both undoped silicon dioxide and silicon nitride. Thus, undoped silicon dioxide and silicon nitride may be employed as etch stops in dry etch processes which utilize the C2HxFy-containing etchant. C2HxFy may be employed as either a primary etchant or as an additive to another etchant or etchant mixture. Semiconductor devices (10) that include structures that have been patterned with an etchant of the present invention or in accordance with the method of the present invention are also disclosed. Specifically, the present invention includes semiconductor devices (10) including doped silicon oxide structures (24) with substantially vertical sidewalls (34) and adjacent undoped silicon oxide or silicon nitride structures (36) exposed adjacent the sidewall (34).

公开(公告)号：EP1004139A1

公开(公告)日：2000-05-31

申请号：EP98906417.5

申请日：1998-02-16

申请人： MICRON TECHNOLOGY, INC.

发明人： KO, Kei-Yu

IPC分类号： H01L21/302 ,  H01L21/311 ,  H01L21/768

CPC分类号： H01L21/76802 ,  H01L21/31116

摘要： The present invention relates to a process for selectively plasma etching a structure upon a semiconductor substrate (12) to form designated topographical structure thereon utilizing an undoped silicon dioxide layer (22) as an etch stop. In one embodiment, a substantially undoped silicon dioxide layer (22) is formed upon a layer of semiconductor material (12). A doped silicon dioxide layer (30) is then formed upon said undoped silicon dioxide layer (16). The doped silicon dioxide layer (30) is etched to create the topographical structure. The etch has a material removal rate that is at least 10 times higher for doped silicon dioxide (30) than for undoped silicon dioxide (16) or the semiconductor material.