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公开(公告)号：EP1057206B1
公开(公告)日：2011-05-11
申请号：EP99908542.6
申请日：1999-02-26
CPC分类号： H01J37/32091 , H01J37/321 , H01J37/32183 , H05H1/46
摘要： A plasma reactor comprises an electromagnetic energy source coupled to a radiator through first and second variable impedance networks. The plasma reactor includes a chamber having a dielectric window that is proximate to the radiator. A shield is positioned between the radiator and the dielectric window. The shield substantially covers a surface of the radiator near the dielectric window. A portion of the radiator that is not covered by the shield is proximate to a conductive wall of the chamber. Plasma reactor operation includes the following steps: a plasma is ignited in a chamber with substantially capacitive electric energy coupled from the radiator; a variable impedance network is tuned so that the capacitive electric energy coupled into the chamber is diminished; the plasma is then powered with substantially magnetic energy.
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公开(公告)号：EP1561239A2
公开(公告)日：2005-08-10
申请号：EP03783399.3
申请日：2003-11-12
IPC分类号： H01L21/285
CPC分类号： H01L21/0228 , C23C16/38 , C23C16/403 , C23C16/45542 , C23C16/515 , H01L21/02178 , H01L21/02183 , H01L21/02186 , H01L21/02205 , H01L21/02274 , H01L21/28562 , H01L21/3141 , H01L21/31616 , H01L21/31683 , H01L21/76841
摘要： A first precursor gas is flowed to the substrate within the chamber effective to form a first monolayer on the substrate. A second precursor gas different in composition from the first precursor gas is flowed to the first monolayer within the chamber under surface microwave plasma conditions within the chamber effective to react with the first monolayer and form a second monolayer on the substrate which is different in composition from the first monolayer. The second monolayer includes components of the first monolayer and the second precursor. In one implementation, the first and second precursor flowings are successively repeated effective to form a mass of material on the substrate of the second monolayer composition. Additional and other implementations are contemplated.
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公开(公告)号：EP1021824A1
公开(公告)日：2000-07-26
申请号：EP98924839.8
申请日：1998-05-21
IPC分类号： H01L21/302 , B05D3/00 , B05D3/12 , H01B13/00 , B44C1/22 , H01L21/3105 , H01L21/768
CPC分类号： H01L21/31053
摘要： A method of manufacturing semiconductor devices using an improved chemical mechanical planarization processes for the planarization of the surfaces (24) of the wafer (60) on which the semiconductor devices (22) are formed. The improved chemical mechanical planarization process includes the formation of a flat planar surface from a deformable coating (30) on the surface of the wafer filling in between the surface irregularities prior to the planarization of the surface through chemical mechanical planarization process.
摘要翻译： 一种使用改进的化学机械平坦化工艺制造半导体器件的方法，用于平坦化在其上形成半导体器件（22）的晶片（60）的表面（24）。 改进的化学机械平坦化工艺包括在通过化学机械平坦化工艺对表面进行平面化之前填充在表面不规则处之间的晶片表面上的可变形涂层（30）形成平坦平坦表面。
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公开(公告)号：EP1561239B1
公开(公告)日：2011-04-27
申请号：EP03783399.3
申请日：2003-11-12
IPC分类号： H01L21/285
CPC分类号： H01L21/0228 , C23C16/38 , C23C16/403 , C23C16/45542 , C23C16/515 , H01L21/02178 , H01L21/02183 , H01L21/02186 , H01L21/02205 , H01L21/02274 , H01L21/28562 , H01L21/3141 , H01L21/31616 , H01L21/31683 , H01L21/76841
摘要： A first precursor gas is flowed to the substrate within the chamber effective to form a first monolayer on the substrate. A second precursor gas different in composition from the first precursor gas is flowed to the first monolayer within the chamber under surface microwave plasma conditions within the chamber effective to react with the first monolayer and form a second monolayer on the substrate which is different in composition from the first monolayer. The second monolayer includes components of the first monolayer and the second precursor. In one implementation, the first and second precursor flowings are successively repeated effective to form a mass of material on the substrate of the second monolayer composition. Additional and other implementations are contemplated.
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5.发明授权PROCESS FOR SELECTIVELY ETCHING DOPED SILICON DIOXIDE OVER UNDOPED SILICON DIOXIDE 有权过程，以未掺杂的氧化硅掺杂的二氧化硅的选择蚀刻
公开(公告)号：EP1297564B1
公开(公告)日：2008-09-17
申请号：EP01956164.6
申请日：2001-07-05
发明人： KO, Kei-Yu , LI, Li , BLALOCK, Guy, T.
IPC分类号： H01L21/311
CPC分类号： H01L21/76897 , H01L21/31116 , H01L21/76802
摘要： An etchant including C2HxFy, where x is an integer from two to five, inclusive, where y is an integer from one to four, inclusive, and where x plus y equals six. The etchant etches doped silicon dioxide with selectivity over both undoped silicon dioxide and silicon nitride. Thus, undoped silicon dioxide and silicon nitride may be employed as etch stops in dry etch processes which utilize the C2HxFy-containing etchant. C2HxFy may be employed as either a primary etchant or as an additive to another etchant or etchant mixture. Semiconductor devices (10) that include structures that have been patterned with an etchant of the present invention or in accordance with the method of the present invention are also disclosed. Specifically, the present invention includes semiconductor devices (10) including doped silicon oxide structures (24) with substantially vertical sidewalls (34) and adjacent undoped silicon oxide or silicon nitride structures (36) exposed adjacent the sidewall (34).
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6.发明公开PROCESS FOR SELECTIVELY ETCHING DOPED SILICON DIOXIDE OVER UNDOPED SILICON DIOXIDE AND SILICON NITRIDE 有权过程，以未掺杂的氧化硅掺杂的二氧化硅的选择蚀刻
公开(公告)号：EP1297564A2
公开(公告)日：2003-04-02
申请号：EP01956164.6
申请日：2001-07-05
发明人： KO, Kei-Yu , LI, Li , BLALOCK, Guy, T.
IPC分类号： H01L21/311
CPC分类号： H01L21/76897 , H01L21/31116 , H01L21/76802
摘要： An etchant including C2HxFy, where x is an integer from two to five, inclusive, where y is an integer from one to four, inclusive, and where x plus y equals six. The etchant etches doped silicon dioxide with selectivity over both undoped silicon dioxide and silicon nitride. Thus, undoped silicon dioxide and silicon nitride may be employed as etch stops in dry etch processes which utilize the C2HxFy-containing etchant. C2HxFy may be employed as either a primary etchant or as an additive to another etchant or etchant mixture. Semiconductor devices (10) that include structures that have been patterned with an etchant of the present invention or in accordance with the method of the present invention are also disclosed. Specifically, the present invention includes semiconductor devices (10) including doped silicon oxide structures (24) with substantially vertical sidewalls (34) and adjacent undoped silicon oxide or silicon nitride structures (36) exposed adjacent the sidewall (34).
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7.发明公开PLASMA REACTOR WITH ELECTRODE ARRANGEMENT FOR PROVIDING A GROUNDING PATH FOR THE PLASMA, AND METHOD OF MANUFACTURING THE SAME 审中-公开与ELEKTRODENANORNUNG等离子体反应器用于产生地球路径血浆和方法生产同样
公开(公告)号：EP1108265A1
公开(公告)日：2001-06-20
申请号：EP99943939.1
申请日：1999-08-26
IPC分类号： H01J37/32
CPC分类号： H01J37/32477 , H01J37/321
摘要： Plasma processing tools, dual source plasma etchers, and etching methods are described. In one embodiments, a processing chamber (206) is provided having an interior base and an interior sidewall (246) joined with the base. A generally planar inductive source (306) is mounted proximate the chamber. A dielectric liner (326) is disposed within the chamber over the interior sidewall with the liner being received over less than an entirety of the interior sidewall. In a preferred embodiment, the interior sidewall has a groundable portion and the dielectric liner has a passageway (346) positioned to expose the groundable interior sidewall portion. Subsequently, a plasma developed within the chamber is disposed along a grounding path which extends to the exposed interior sidewall. In another preferred embodiment, the dielectric liner is removably mounted within the processing chamber.
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8.发明授权CAPACITOR CONSTRUCTIONS, RUGGED SILICON-CONTAINING SURFACES, AND METHODS OF FORMING RUGGED SILICON-CONTAINING SURFACES 有权电容器结构，其制造粗糙含硅曲面粗糙的含硅表面及其方法
公开(公告)号：EP1668678B1
公开(公告)日：2011-03-23
申请号：EP04782390.1
申请日：2004-08-26
IPC分类号： H01L21/02 , H01L21/8242
CPC分类号： H01L27/10852 , H01L28/84 , Y10S438/964
摘要： The invention encompasses a method of forming a rugged silicon-containing surface. A layer comprising amorphous silicon is provided within a reaction chamber at a first temperature. The temperature is increased to a second temperature at least 400 C higher than the first temperature while flowing at least one hydrogen isotope into the chamber. After the temperature reaches the second temperature, the layer is seeded with seed crystals. The seeded layer is then annealed to form a rugged silicon-containing surface. The rugged silicon-containing surface can be incorporated into a capacitor construction. The capacitor construction can be incorporated into a DRAM cell, and the DRAM cell can be utilized in an electronic system.
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9.发明公开CAPACITOR CONSTRUCTIONS, RUGGED SILICON-CONTAINING SURFACES, AND METHODS OF FORMING RUGGED SILICON-CONTAINING SURFACES 有权电容器结构，其制造粗糙含硅曲面粗糙的含硅表面及其方法
公开(公告)号：EP1668678A1
公开(公告)日：2006-06-14
申请号：EP04782390.1
申请日：2004-08-26
IPC分类号： H01L21/02 , H01L21/8242
CPC分类号： H01L27/10852 , H01L28/84 , Y10S438/964
摘要： The invention encompasses a method of forming a rugged silicon-containing surface. A layer comprising amorphous silicon is provided within a reaction chamber at a first temperature. The temperature is increased to a second temperature at least 400 C higher than the first temperature while flowing at least one hydrogen isotope into the chamber. After the temperature reaches the second temperature, the layer is seeded with seed crystals. The seeded layer is then annealed to form a rugged silicon-containing surface. The rugged silicon-containing surface can be incorporated into a capacitor construction. The capacitor construction can be incorporated into a DRAM cell, and the DRAM cell can be utilized in an electronic system.
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公开(公告)号：EP1021824B1
公开(公告)日：2003-12-17
申请号：EP98924839.8
申请日：1998-05-21
IPC分类号： H01L21/302 , B05D3/00 , B05D3/12 , H01B13/00 , B44C1/22 , H01L21/3105 , H01L21/768
CPC分类号： H01L21/31053
摘要： A method of manufacturing semiconductor devices using an improved chemical mechanical planarization processes for the planarization of the surfaces (24) of the wafer (60) on which the semiconductor devices (22) are formed. The improved chemical mechanical planarization process includes the formation of a flat planar surface from a deformable coating (30) on the surface of the wafer filling in between the surface irregularities prior to the planarization of the surface through chemical mechanical planarization process.
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