公开(公告)号：EP3100357A1

公开(公告)日：2016-12-07

申请号：EP15744089.2

申请日：2015-01-14

申请人： Microsemi Semiconductor ULC

发明人： MILIJEVIC, Slobodan

IPC分类号： H03L7/07 ,  H03L7/099 ,  H04L7/00

CPC分类号： H03L7/087 ,  H03L7/07 ,  H03L7/0805 ,  H03L7/0807 ,  H03L7/0991 ,  H03L7/22

摘要： A double phase-locked has a first phase-locked loop including a first narrowband loop filter configured to reduce phase noise in a first input clock, and a second phase-locked loop including a second loop filter configured to receive a second input clock from a stable clock source. The second clock has a frequency close to said first clock. The first loop has a bandwidth at least an order of magnitude less than the second loop. A coupler couples the first second phase-locked loops to provide a common output. The double phase locked loop can be used, for example, to provide time-of-day information in wireless networks or as a fine filter for cleaning phase noise from clock signals recovered over telecom/datacom networks