-
公开(公告)号：EP4459389A1
公开(公告)日：2024-11-06
申请号：EP23315151.3
申请日：2023-05-02
发明人： Bouttier, Arnaud , Bechihi, Adel
IPC分类号： G05B9/02
摘要： The description proposes a method to control an agent (AGT) operating at least one actuator according to commands repeatedly received from a controller (CTLR), said agent receiving repeatedly measurement data from at least one sensor sensing an environment of the actuator, said measurement data defining, at an iteration k, a current state x k n of the actuator's environment resulting from the application by the actuator of a nominal command u k − 1 n at a previous iteration k -1, said nominal command u k − 1 n at previous iteration k -1 being initially:
- computed by the controller (CTLR) based on a current state x k − 1 n of the actuator's environment defined at least by measurement data acquired by the sensor during said previous iteration k -1, and
- transmitted by the controller (CTLR) to the agent (AGT) to be applied by the actuator,
Wherein the controller (CTLR), at each iteration k:
- computes, in addition to said nominal command u k n , a switching command u k + 1 c based at least on the current state x k n at said iteration k, and
- transmits to the agent (AGT) said switching command u k + 1 c along with said nominal command u k n , said switching command u k + 1 c being intended to be used by the agent to operate the actuator in case no command is received by the agent following the application of the nominal command u k n of iteration k.-
2.发明公开Parallelized hardware architecture to compute different sizes of DFT 审中-公开平行五金建筑师Zere Berechnung von DFTs verschidenerLänge
公开(公告)号：EP2144174A1
公开(公告)日：2010-01-13
申请号：EP08159859.1
申请日：2008-07-07
IPC分类号： G06F17/14
CPC分类号： G06F17/144 , G06F17/142
摘要： To speed up the computation the invention proposes to use two computation cores in parallel to compute a DFT. Data are dispatched between the two cores according to the even and odd lines of the PFA Ruritanian mapping matrix. Separate storage means are used for each core and means are provided to exchange data between the two separate storage means between the radix computation steps.
摘要翻译： 为了加快计算，本发明提出并行使用两个计算核心来计算DFT。 根据PFA Ruritanian映射矩阵的偶数和奇数行，在两个核之间调度数据。 每个核心使用单独的存储装置，并且提供装置以在基数计算步骤之间在两个分开的存储装置之间交换数据。
-
3.发明授权
公开(公告)号：EP2670102B1
公开(公告)日：2016-03-30
申请号：EP12170264.1
申请日：2012-05-31
发明人： Bouttier, Arnaud
IPC分类号： H04L27/26
CPC分类号： H04L27/2659 , H04L27/2665 , H04L27/2671
-
4.发明公开
公开(公告)号：EP2670102A1
公开(公告)日：2013-12-04
申请号：EP12170264.1
申请日：2012-05-31
发明人： Bouttier, Arnaud
IPC分类号： H04L27/26
CPC分类号： H04L27/2659 , H04L27/2665 , H04L27/2671
摘要： The present invention concerns a device for synchronizing a receiver on received preamble symbol modulated by an orthogonal frequency division multiplexing scheme. The device comprises:
- means for executing a coarse synchronization which provides an estimate of a first time offset and fractional frequency offset,
- means for removing the fractional frequency offset from the preamble symbol,
- means for performing an OFDM demodulation on the preamble symbol on which the fractional frequency offset is removed,
- means for removing from the subcarriers of the demodulated preamble symbol the effect of a phase shift keying modulation,
- means for performing an IDFT on the demodulated preamble symbol on which effect of a modulation wherein at least the phase on subcarriers on which preamble symbol is mapped is modified according to the binary information value of the preamble sequence carried by the subcarrier,
- means for determining a second time offset from the output of the inverse discrete Fourier transform,
- means for compensating the effect of the time offset for next received orthogonal division multiplexing symbol using the second time offset.-
公开(公告)号：EP2230806B1
公开(公告)日：2011-11-23
申请号：EP09155634.0
申请日：2009-03-19
CPC分类号： H04L25/03038 , H03H17/0225 , H03H17/0227 , H03H17/06 , H04L25/022 , H04L2025/03471 , H04L2025/03585
-
6.发明公开Method and device for filtering with FIR filters 有权Verfahren und Vorrichtung zur Signalfilterung mit FIR-Filtern
公开(公告)号：EP2230806A1
公开(公告)日：2010-09-22
申请号：EP09155634.0
申请日：2009-03-19
CPC分类号： H04L25/03038 , H03H17/0225 , H03H17/0227 , H03H17/06 , H04L25/022 , H04L2025/03471 , H04L2025/03585
摘要： It is proposed a method and device for implementing finite impulse response filters, called FIR filters where filtering is applied on finite sets of samples.
This method deals more accurately with the transient mode computation. It is based on a variable width of the filter used to compute the transient mode. Moreover the proposed solution is easy to implement using only L + 1 real or complex multipliers for the stationary mode as well as the transient mode.摘要翻译： 提出了一种用于实现有限脉冲响应滤波器的方法和装置，称为FIR滤波器，其中滤波被应用于有限样本集合。 该方法更准确地处理瞬态模式计算。 它基于用于计算瞬态模式的滤波器的可变宽度。 此外，所提出的解决方案仅对于固定模式以及瞬态模式，仅使用L + 1实数或复数乘法器容易实现。
-
7.发明公开Hardware architecture to compute different sizes of DFT 审中-公开硬件建筑师Zere Berechnung von DFTs verschiedenerLänge
公开(公告)号：EP2144173A1
公开(公告)日：2010-01-13
申请号：EP08159854.2
申请日：2008-07-07
IPC分类号： G06F17/14
CPC分类号： G06F17/142 , G06F17/144
摘要： The invention presented in this document deals with the hardware implementation of the General Prime Factor Algorithm (GPFA) on integrated circuits on the purpose of minimizing both the complexity and the latency. It proposes a device to implement discrete Fourier transforms in a self-sorting and in-place manner for composite sizes that can be factorized into the product of mutually prime numbers, where some or all of these numbers can expressed as the power of a given base number. The described DFT device is able to dynamically changing the size of the DFT between two consecutive transforms. Derivations of the proposed algorithm are presented to further reduce the latency at the expense of an increased complexity.
摘要翻译： 本文中提出的发明涉及集成电路上的通用优先因子算法（GPFA）的硬件实现，以便最小化复杂性和延迟。 它提出了一种用于以自分类和就地方式实现离散傅立叶变换的装置，用于复合尺寸，其可以被分解为相互质数的乘积，其中这些数字中的一些或全部可以表示为给定基数的幂 数。 所描述的DFT设备能够在两个连续的变换之间动态地改变DFT的大小。 提出了所提出的算法的推导，以进一步降低延迟，牺牲增加的复杂性。
-
-
-
-
-
-
搜索结果
7 条记录 (耗时 0.014 秒)
