公开(公告)号：EP0347759B1

公开(公告)日：1994-08-10

申请号：EP89110915.9

申请日：1989-06-16

申请人： NATIONAL SEMICONDUCTOR CORPORATION

发明人： Proebsting, Robert J.

IPC分类号： H03K19/017

CPC分类号： H03K19/01707 ,  G11C8/06 ,  G11C8/18 ,  H03K5/1504 ,  H03K5/1534 ,  H03K19/01721 ,  H03K19/018521

公开(公告)号：EP0596864A2

公开(公告)日：1994-05-11

申请号：EP94100767.6

申请日：1989-06-16

申请人： NATIONAL SEMICONDUCTOR CORPORATION

发明人： Proebsting, Robert J.

IPC分类号： H03K19/017 ,  H03K5/153

CPC分类号： H03K19/01707 ,  G11C8/06 ,  G11C8/18 ,  H03K5/1504 ,  H03K5/1534 ,  H03K19/01721 ,  H03K19/018521

摘要： A speed enhancement technique for CMOS circuits is disclosed. In the series of logic stages, nodes in the signal path of a pulse are set by preceding logic stages, then reset by feedback from a subsequent logic stage. This eliminates the capacitive burden of resetting any given node from the input signal to allow substantially all of the input signal to be employed in setting the nodes to an active state rather than wasting half the signal in turning off the reset path. The technique is illustrated as applied to RAM circuits.

摘要翻译： 公开了一种用于CMOS电路的速度增强技术。 在一系列逻辑级中，脉冲信号路径中的节点由先前的逻辑级设置，然后通过后续逻辑级的反馈进行复位。 这消除了从输入信号复位任何给定节点的电容性负担，以允许基本上将所有输入信号用于将节点设置为活动状态，而不是在关闭复位路径时浪费信号的一半。 该技术被应用于RAM电路。

公开(公告)号：EP0347759A3

公开(公告)日：1990-04-18

申请号：EP89110915.9

申请日：1989-06-16

申请人： NATIONAL SEMICONDUCTOR CORPORATION

发明人： Proebsting, Robert J.

IPC分类号： H03K19/017

CPC分类号： H03K19/01707 ,  G11C8/06 ,  G11C8/18 ,  H03K5/1504 ,  H03K5/1534 ,  H03K19/01721 ,  H03K19/018521

摘要： A speed enhancement technique for CMOS circuits is disclosed. In the series of logic stages, nodes in the signal path of a pulse are set by preceding logic stages, then reset by feedback from a subsequent logic stage. This eliminates the capacitive burden of resetting any given node from the input signal to allow substantially all of the input signal to be employed in setting the nodes to an active state rather than wasting half the signal in turning off the reset path. The technique is illustrated as applied to RAM circuits.

公开(公告)号：EP0347759A2

公开(公告)日：1989-12-27

申请号：EP89110915.9

申请日：1989-06-16

申请人： NATIONAL SEMICONDUCTOR CORPORATION

发明人： Proebsting, Robert J.

IPC分类号： H03K19/017

CPC分类号： H03K19/01707 ,  G11C8/06 ,  G11C8/18 ,  H03K5/1504 ,  H03K5/1534 ,  H03K19/01721 ,  H03K19/018521

摘要： A speed enhancement technique for CMOS circuits is disclosed. In the series of logic stages, nodes in the signal path of a pulse are set by preceding logic stages, then reset by feedback from a subsequent logic stage. This eliminates the capacitive burden of resetting any given node from the input signal to allow substantially all of the input signal to be employed in setting the nodes to an active state rather than wasting half the signal in turning off the reset path. The technique is illustrated as applied to RAM circuits.

摘要翻译： 公开了一种用于CMOS电路的速度增强技术。 在一系列逻辑级中，脉冲信号路径中的节点由先前的逻辑级设置，然后通过后续逻辑级的反馈进行复位。 这消除了从输入信号复位任何给定节点的电容性负担，以允许基本上将所有输入信号用于将节点设置为活动状态，而不是在关闭复位路径时浪费信号的一半。 该技术被应用于RAM电路。

公开(公告)号：EP0596864A3

公开(公告)日：1994-06-08

申请号：EP94100767.6

申请日：1989-06-16

申请人： NATIONAL SEMICONDUCTOR CORPORATION

发明人： Proebsting, Robert J.

IPC分类号： H03K19/017 ,  H03K5/153

CPC分类号： H03K19/01707 ,  G11C8/06 ,  G11C8/18 ,  H03K5/1504 ,  H03K5/1534 ,  H03K19/01721 ,  H03K19/018521

摘要： A speed enhancement technique for CMOS circuits is disclosed. In the series of logic stages, nodes in the signal path of a pulse are set by preceding logic stages, then reset by feedback from a subsequent logic stage. This eliminates the capacitive burden of resetting any given node from the input signal to allow substantially all of the input signal to be employed in setting the nodes to an active state rather than wasting half the signal in turning off the reset path. The technique is illustrated as applied to RAM circuits.

摘要翻译： 公开了一种用于CMOS电路的速度增强技术。 在一系列逻辑级中，脉冲信号路径中的节点由前面的逻辑级设置，然后通过后续逻辑级的反馈进行复位。 这消除了从输入信号复位任何给定节点的电容性负担，以允许基本上将所有输入信号用于将节点设置为活动状态，而不是在关闭复位路径时浪费信号的一半。 该技术被应用于RAM电路。