公开(公告)号：EP0908889A3

公开(公告)日：1999-04-28

申请号：EP98117290.1

申请日：1998-09-11

Applicant: NEC CORPORATION

Inventor： Maesako, Taketo ,  Yamamoto, Kouki ,  Matsui, Yoshinori ,  Sakakibara, Kenichi

IPC: G11C7/00

CPC classification number: G11C7/103 ,  G01R31/31715

Abstract: A semiconductor integrated circuit device is comprised a main memory portion, a sub memory portion composed of a plurality of memory cell groups and a bi-directional data transfer circuit provided between the main memory portion and the sub memory portion, wherein power source voltages of the main memory portion and the sub memory portion are different from each other. Therefore, the semiconductor integrated circuit device of the present invention has a main memory suitable for being accessed from a plurality of data processors.

公开(公告)号：EP0908886A2

公开(公告)日：1999-04-14

申请号：EP98117281.0

申请日：1998-09-11

Applicant: NEC CORPORATION

Inventor： Maesako, Taketo ,  Yamamoto, Kouki ,  Matsui, Yoshinori ,  Sakakibara, Kenichi

IPC: G11C7/00

CPC classification number: G11C7/103 ,  G11C7/10 ,  G11C8/16 ,  G11C11/005

Abstract: A semiconductor integrated circuit device is comprised a main memory portion constructed with memory cells arranged in a plurality of rows and in a plurality of columns, a sub memory portion constructed with a plurality of memory cells arranged in a plurality of rows and in a plurality of columns and a bi-directional data transfer circuit for connecting the main memory portion and the sub memory portion through data transfer bus lines, respectively, wherein the data transfer bus lines in a memory cell area of the main memory portion are arranged in parallel to bit lines in a column direction and connected to the bit lines through a column selection circuit. Therefore, the semiconductor integrated circuit device of the present invention has a main memory suitable for being accessed from a plurality of data processors.

Abstract translation: 半导体集成电路器件包括：主存储器部分，其构造为以多行和多列布置的存储单元;子存储器部分，其构造有多个存储单元，多个存储单元被布置成多行和多个 列和用于分别通过数据传输总线连接主存储器部分和副存储器部分的双向数据传输电路，其中主存储器部分的存储器单元区域中的数据传输总线线路与位 线列，并通过列选择电路连接到位线。 因此，本发明的半导体集成电路装置具有适于从多个数据处理器访问的主存储器。

公开(公告)号：EP0637033A3

公开(公告)日：1996-12-04

申请号：EP94111639.4

申请日：1994-07-26

Applicant: NEC CORPORATION

Inventor： Matsui, Yoshinori

IPC: G11C7/00 ,  G11C11/409

CPC classification number: G11C11/4096 ,  G11C7/1048

Abstract: A column selector (34) of a dynamic random access memory device is implemented by a plurality of switching circuits (341-34m) for transferring a potential difference from a sense amplifier (SA1-SAm) to a shared data line pair (DL1/DL2), and one of the switching circuits selectively discharge the data lines (DL1/DL2) of the pair to a ground voltage line (GND) for transferring the potential difference to the shared data line pair, wherein a potential control circuit (37) is coupled between the switching circuits and the ground voltage line for decreasing the current (I) flowing from the data line to the ground voltage line after production of an output data signal (Dout), thereby decreasing the current consumption.

公开(公告)号：EP0908888A3

公开(公告)日：1999-04-28

申请号：EP98117288.5

申请日：1998-09-11

Applicant: NEC CORPORATION

Inventor： Maesako, Taketo ,  Yamamoto, Kouki ,  Matsui, Yoshinori ,  Sakakibara, Kenichi

IPC: G11C7/00

CPC classification number: G11C7/103

Abstract: A semiconductor integrated circuit device is comprised a main memory portion, a sub memory portion composed of a plurality of memory cell groups and a bi-directional data transfer circuit provided between the main memory device and said sub memory portion, wherein a bi-directional data transfer between an arbitrary area of said main memory portion and the plurality of the memory cell groups and a read or write operation are performed simultaneously. Therefore, the semiconductor integrated circuit device of the present invention has a main memory suitable for being accessed from a plurality of data processors.

Abstract translation: 半导体集成电路器件包括主存储器部分，由多个存储器单元组构成的子存储器部分以及设置在主存储器器件和所述子存储器部分之间的双向数据传输电路，其中双向数据 在所述主存储器部分的任意区域和所述多个存储器单元组之间的传输以及读或写操作被同时执行。 因此，本发明的半导体集成电路器件具有适合于从多个数据处理器访问的主存储器。

公开(公告)号：EP0908888A2

公开(公告)日：1999-04-14

申请号：EP98117288.5

申请日：1998-09-11

Applicant: NEC CORPORATION

Inventor： Maesako, Taketo ,  Yamamoto, Kouki ,  Matsui, Yoshinori ,  Sakakibara, Kenichi

IPC: G11C7/00

CPC classification number: G11C7/103

Abstract: A semiconductor integrated circuit device is comprised a main memory portion, a sub memory portion composed of a plurality of memory cell groups and a bi-directional data transfer circuit provided between the main memory device and said sub memory portion, wherein a bi-directional data transfer between an arbitrary area of said main memory portion and the plurality of the memory cell groups and a read or write operation are performed simultaneously. Therefore, the semiconductor integrated circuit device of the present invention has a main memory suitable for being accessed from a plurality of data processors.

Abstract translation: 半导体集成电路器件包括主存储器部分，由多个存储单元组组成的子存储器部分和设置在主存储器件和所述副存储器部分之间的双向数据传输电路，其中双向数据 同时执行所述主存储部分的任意区域与多个存储单元组之间的转移以及读或写操作。 因此，本发明的半导体集成电路装置具有适于从多个数据处理器访问的主存储器。

公开(公告)号：EP0590608B1

公开(公告)日：1998-09-02

申请号：EP93115647.5

申请日：1993-09-28

Applicant: NEC CORPORATION

Inventor： Matsui, Yoshinori

IPC: G06F11/20

CPC classification number: G11C29/846

公开(公告)号：EP0908890A3

公开(公告)日：1999-04-28

申请号：EP98117292.7

申请日：1998-09-11

Applicant: NEC CORPORATION

Inventor： Maesako, Taketo ,  Yamamoto, Kouki ,  Matsui, Yoshinori ,  Sakakibara, Kenichi

IPC: G11C7/00

CPC classification number: G11C7/1072 ,  G11C7/103 ,  G11C7/1045 ,  G11C7/1075 ,  G11C11/005

Abstract: A semiconductor integrated circuit device is comprised a main memory portion and a sub memory portion composed of a plurality of memory cell groups, wherein a bi-directional data transfer is performed between an arbitrary area of the main memory portion and each of the plurality of the memory cell groups and the plurality of the memory cell groups function as independent cache memories, respectively. Therefore, the semiconductor integrated circuit device of the present invention has a main memory suitable for being accessed from a plurality of data processors.

Abstract translation: 一种半导体集成电路器件包括主存储器部分和由多个存储器单元组构成的子存储器部分，其中在主存储器部分的任意区域与多个存储器单元中的每一个之间执行双向数据传输 存储单元组和多个存储单元组分别用作独立的高速缓存存储器。 因此，本发明的半导体集成电路器件具有适合于从多个数据处理器访问的主存储器。

公开(公告)号：EP0908887A2

公开(公告)日：1999-04-14

申请号：EP98117287.7

申请日：1998-09-11

Applicant: NEC CORPORATION

Inventor： Maesako, Taketo ,  Yamamoto, Kouki ,  Matsui, Yoshinori ,  Sakakibara, Kenichi

IPC: G11C7/00

CPC classification number: G11C7/103

Abstract: A semiconductor integrated circuit device is comprised a main memory portion composed of a plurality of memory cells arranged in a plurality of rows and in a plurality of columns, a sub memory portion composed of a plurality of memory cells arranged in a plurality of rows and in a plurality of columns, a bi-directional data transfer circuit for connecting the main memory portion and the sub memory portion through data transfer bus lines, respectively, the sub memory portion being constituted with a plurality of memory cell groups, and a plurality of registers provided such that different data input/output modes are set independently for the plurality of the memory cell groups. Therefore, the semiconductor integrated circuit device of the present invention has a main memory suitable for being accessed from a plurality of data processors.

Abstract translation: 一种半导体集成电路器件包括：主存储器部分，其由以多行排列的多个存储单元组成;多个存储单元，多个存储单元组成的多个存储器单元， 多个列，分别通过数据传输总线连接主存储器部分和副存储器部分的双向数据传输电路，子存储器部分分别由多个存储单元组构成，以及多个寄存器 被提供为使得针对多个存储单元组独立设置不同的数据输入/输出模式。 因此，本发明的半导体集成电路装置具有适于从多个数据处理器访问的主存储器。

公开(公告)号：EP0637033A2

公开(公告)日：1995-02-01

申请号：EP94111639.4

申请日：1994-07-26

Applicant: NEC CORPORATION

Inventor： Matsui, Yoshinori

IPC: G11C7/00 ,  G11C11/409

CPC classification number: G11C11/4096 ,  G11C7/1048

Abstract: A column selector (34) of a dynamic random access memory device is implemented by a plurality of switching circuits (341-34m) for transferring a potential difference from a sense amplifier (SA1-SAm) to a shared data line pair (DL1/DL2), and one of the switching circuits selectively discharge the data lines (DL1/DL2) of the pair to a ground voltage line (GND) for transferring the potential difference to the shared data line pair, wherein a potential control circuit (37) is coupled between the switching circuits and the ground voltage line for decreasing the current (I) flowing from the data line to the ground voltage line after production of an output data signal (Dout), thereby decreasing the current consumption.

Abstract translation: 动态随机存取存储器件的列选择器（34）由用于将读出放大器（SA1-SAm）的电位差传送到共享数据线对（DL1 / DL2）的多个开关电路（341-34m）来实现 ），并且其中一个开关电路选择性地将该对的数据线（DL1 / DL2）放电到用于将电位差传送到共享数据线对的地电压线（GND），其中电位控制电路（37）是 耦合在开关电路和地电压线之间，用于减少在产生输出数据信号（Dout）之后从数据线流向地电压线的电流（I），从而降低电流消耗。

公开(公告)号：EP0590608A2

公开(公告)日：1994-04-06

申请号：EP93115647.5

申请日：1993-09-28

Applicant: NEC CORPORATION

Inventor： Matsui, Yoshinori

IPC: G06F11/20

CPC classification number: G11C29/846

Abstract: The semiconductor memory device includes at least one pair of redundant digit lines (RD,RDb), first input/output lines (IO,IOb) connected to a pair of digit lines (D,Db) via a respective sense amplifier (SA) and a switch (SW), second input/output lines (IO',IOb')connected to the redundant digit line pair (RD,RDb) via a sense amplifier (RSA) and switch (RSW), and selective amplifier means (IOSW, IOSW`, RIOSW, RIOSW`) for amplifying second input/output lines when redundant digit lines are selected.
With this configuration, even when the redundant digit line pair is substituted for the digit line pair, it is possible to execute the redundancy operation by mere translation between these input/output line pairs.

Abstract translation: 半导体存储器件包括至少一对经由相应读出放大器（SA）连接到一对数字线（D，Db）的冗余数字线（RD，RDb），第一输入/输出线（IO，IOb）和 经由读出放大器（RSA）和开关（RSW）连接到冗余数字线对（RD，RDb）的开关（SW），第二输入/输出线路（IO'，IOb'）以及选择性放大器装置（IOSW， IOSW`，RIOSW，RIOSW`），用于在选择冗余数字线时放大第二输入/输出线。 利用这种配置，即使冗余数字线对代替数字线对，也可以通过这些输入/输出线对之间的简单转换来执行冗余操作。