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    METHODS AND SYSTEMS FOR NONVOLATILE MEMORY DATA MANAGEMENT
    2.
    发明公开
    METHODS AND SYSTEMS FOR NONVOLATILE MEMORY DATA MANAGEMENT 有权
    VERFAHREN UND SYSTEMEFÜRNICHTFLÜCHTIGESPEICHERDATENVERWALTUNG

    公开(公告)号：EP3098814A1

    公开(公告)日：2016-11-30

    申请号：EP16152561.3

    申请日：2016-01-25

    申请人： Winbond Electronics Corp.

    发明人： Lien, Chuen-Der ,  Shieh, Ming-Huei ,  Lin, Chi-shun (Elbert)

    IPC分类号： G11C13/00 ,  G11C7/04 ,  G11C11/00

    CPC分类号： G06F11/1068 ,  G06F3/0619 ,  G06F3/064 ,  G06F3/0655 ,  G06F3/0679 ,  G06F3/0688 ,  G06F11/1072 ,  G11C5/148 ,  G11C7/04 ,  G11C7/20 ,  G11C11/005 ,  G11C11/1695 ,  G11C13/0002 ,  G11C13/0033 ,  G11C13/0059 ,  G11C14/0036 ,  G11C14/0045 ,  G11C29/12 ,  G11C29/52

    摘要： A system includes a first resistive nonvolatile memory array, a second transistor-based nonvolatile memory array and a memory controller. The memory controller is configured to write data of the first resistive nonvolatile memory array together with an indicator bit to the second transistor-based nonvolatile memory array, determine whether the indicator bit is valid in response to a power up of the system after a high-temperature event, a received command after a high-temperature event, a predetermined number of power ups, or a power up or received command after each of a predetermined number of high-temperature events and write back the data stored in the second transistor-based nonvolatile memory array to the first resistive nonvolatile memory array when the indicator bit is valid.

    摘要翻译： 系统包括第一电阻性非易失性存储器阵列，第二晶体管非易失性存储器阵列和存储器控制器。 存储器控制器被配置为将第一电阻性非易失性存储器阵列的数据与指示符位一起写入到第二基于晶体管的非易失性存储器阵列，根据系统的高电平确定指示符位是否有效， 温度事件，在高温事件之后的接收命令，预定数量的功率上升，或者在预定数量的高温事件中的每一个之后的加电或接收命令，并将存储在第二晶体管的数据 当指示符位有效时，非易失性存储器阵列到第一电阻性非易失性存储器阵列。

    One-time programming in reprogrammable memory
    4.
    发明公开
    One-time programming in reprogrammable memory 审中-公开
    一次性编程在可重编程的存储器中

    公开(公告)号：EP2919236A1

    公开(公告)日：2015-09-16

    申请号：EP15157372.2

    申请日：2015-03-03

    申请人： NXP B.V.

    发明人： Vauclair, Marc ,  Teuwen, Philippe

    IPC分类号： G11C16/22 ,  G11C17/16 ,  G11C13/00 ,  G11C7/10 ,  G11C11/00

    CPC分类号： G06F3/0619 ,  G06F3/0652 ,  G06F3/0679 ,  G06F2206/1014 ,  G11C7/1045 ,  G11C11/005 ,  G11C13/0035 ,  G11C13/0059 ,  G11C13/0069 ,  G11C16/22 ,  G11C17/165 ,  G11C2013/0083

    摘要： A portion of a reprogrammable storage device is used to implement permanent data storage. The storage device includes a plurality of electrically erasable memory elements and a controller. The plurality of electrically erasable memory elements are configured to store data. Each memory element is programmable a number of write cycles before reaching a write failure state. The controller is coupled to the plurality of memory elements. The controller includes a receiver and a write engine. The receiver receives an instruction to drive a selected memory element to the write failure state. The write engine repeatedly writes a data value, in a plurality of write operations, to the selected memory element until the write failure state of the selected memory element is established.

    摘要翻译： 可重编程存储设备的一部分用于实现永久数据存储。 存储装置包括多个电可擦除存储器元件和控制器。 多个电可擦除存储器元件被配置为存储数据。 在达到写入失败状态之前，每个存储器元件都可以编程多个写入周期。 控制器耦合到多个存储器元件。 该控制器包括一个接收器和一个写入引擎。 接收器接收指令以将选定的存储器元件驱动到写入失败状态。 写入引擎将多个写入操作中的数据值重复写入选定的存储器元件，直到所选择的存储器元件的写入失败状态被建立。

    MONOLITHIC MULTI-CHANNEL ADAPTABLE STT-MRAM
    5.
    发明公开
    MONOLITHIC MULTI-CHANNEL ADAPTABLE STT-MRAM 审中-公开
    单片多通道可适应STT-MRAM

    公开(公告)号：EP2883230A1

    公开(公告)日：2015-06-17

    申请号：EP13753227.1

    申请日：2013-08-07

    申请人： Qualcomm Incorporated

    发明人： KANG, Seung H. ,  ZHU, Xiaochun

    IPC分类号： G11C29/02 ,  G11C11/16

    CPC分类号： G11C11/16 ,  G11C8/16 ,  G11C11/005 ,  G11C11/1653 ,  G11C29/028

    摘要： A monolithic multi-channel resistive memory includes at least one first bank associated with a first channel and tuned according to first device attributes and/or first circuit attributes. The memory also includes at least one second bank associated with a second channel and tuned according to second device attributes and/or second circuit attributes.

    摘要翻译： 单片多通道电阻式存储器包括与第一通道相关联的至少一个第一存储体并且根据第一设备属性和/或第一电路属性进行调整。 存储器还包括与第二信道相关联的至少一个第二存储体并且根据第二设备属性和/或第二电路属性进行调谐。

    METHOD AND SYSTEM FOR STORING LOGICAL DATA BLOCKS INTO FLASH-BLOCKS IN MULTIPLE NON-VOLATILE MEMORIES WHICH ARE CONNECTED TO AT LEAST ONE COMMON DATA I/O BUS
    7.
    发明授权
    METHOD AND SYSTEM FOR STORING LOGICAL DATA BLOCKS INTO FLASH-BLOCKS IN MULTIPLE NON-VOLATILE MEMORIES WHICH ARE CONNECTED TO AT LEAST ONE COMMON DATA I/O BUS 有权
    方法和系统的几个非易失性存储器存储FLASH块中的数据的逻辑块与至少一个通用数据I / O总线相连

    公开(公告)号：EP1869543B1

    公开(公告)日：2013-03-06

    申请号：EP06725158.7

    申请日：2006-03-20

    申请人： Thomson Licensing

    发明人： WITTENBURG, Jens, Peter ,  BRUNE, Thomas

    IPC分类号： G06F3/06 ,  G06F12/02 ,  G11C29/00 ,  G11C16/10 ,  G11C11/00

    CPC分类号： G06F12/0246 ,  G06F2212/7203 ,  G11C11/005 ,  G11C16/0483 ,  G11C16/10 ,  G11C29/76 ,  Y02D10/13

    摘要： For recording or replaying in real-time digital HDTV signals very fast memories are required. For storage of streaming HD video data NAND flash memory based systems can be used. However, NAND flash memories have a slow write access, and they have unmasked production defects. Write or read operations can be carried out on complete physical data blocks only, and defect data blocks must not be used by the file system. Logical file system blocks are used which are larger than the physical data blocks. According to the invention the error reporting mechanism of the NAND flash memories is exploited. The video data is not only written to the nonvolatile flash memories, but is also written to corresponding buffer slots (LFSB) of a volatile SRAM or DRAM memory operating in parallel. The video data are kept in the volatile memory until the flash memory holding the respective data has reported that its program or write operation succeeded. Once this has taken place, the data within the volatile memory can be overwritten in order to save memory capacity. If the flash memory has reported an error, the respective block (FSBD) of data is marked bad and will not be overwritten until the end of the entire recorded take has been reached. At this time, the marked video data from the volatile memory are copied to spare flash-blocks within the flash memories.

    HYBRID MEMORY DEVICE WITH SINGLE INTERFACE
    8.
    发明公开
    HYBRID MEMORY DEVICE WITH SINGLE INTERFACE 审中-公开
    与单一的界面混合存储设备

    公开(公告)号：EP2025001A4

    公开(公告)日：2010-07-28

    申请号：EP07795704

    申请日：2007-06-01

    申请人： MICROSOFT CORP

    发明人： PANABAKER RUSTON ,  CREASY JACK

    IPC分类号： H01L27/115 ,  G06F12/06

    CPC分类号： G06F12/06 ,  G06F12/0638 ,  G06F2212/2022 ,  G06F2212/205 ,  G11C7/10 ,  G11C8/12 ,  G11C11/005 ,  G11C2207/104

    摘要： Described is a technology by which a memory controller is a component of a hybrid memory device having different types of memory therein (e.g., SDRAM and flash memory), in which the controller operates such that the memory device has only a single memory interface with respect to voltage and access protocols defined for one type of memory. For example, the controller allows a memory device with a standard SDRAM interface to provide access to both SDRAM and non-volatile memory with the non-volatile memory overlaid in one or more designated blocks of the volatile memory address space (or vice-versa). A command protocol maps memory pages to the volatile memory interface address space, for example, permitting a single pin compatible multi-chip package to replace an existing volatile memory device in any computing device that wants to provide non-volatile storage, while only requiring software changes to the device to access the flash.

    SEMICONDUCTOR MEMORY DEVICE
    9.
    发明公开
    SEMICONDUCTOR MEMORY DEVICE 审中-公开
    半导体存储器件

    公开(公告)号：EP2108182A2

    公开(公告)日：2009-10-14

    申请号：EP08835305.7

    申请日：2008-09-30

    申请人： Kabushiki Kaisha Toshiba

    发明人： NAGADOMI, Yasushi ,  TAKASHIMA, Daisaburo ,  HATSUDA, Kosuke

    IPC分类号： G11C16/34 ,  G11C11/406 ,  G06F11/10

    CPC分类号： G11C16/349 ,  G06F11/1068 ,  G11C11/005 ,  G11C16/3431

    摘要： This disclosure concerns a memory including: a first memory region including memory groups including a plurality of memory cells, addresses being respectively allocated for the memory groups, the memory groups respectively being units of data erase operations; a second memory region temporarily storing therein data read from the first memory region or temporarily storing therein data to be written to the first memory region; a read counter storing therein a data read count for each memory group; an error-correcting circuit calculating an error bit count of the read data; and a controller performing a refresh operation, in which the read data stored in one of the memory groups is temporarily stored in the second memory region and is written back the read data to the same memory group, when the error bit count exceeds a first threshold or when the data read count exceeds a second threshold.

    A SECURE NON-VOLATILE MEMORY DEVICE AND A METHOD OF PROTECTING DATA THEREIN
    10.
    发明公开
    A SECURE NON-VOLATILE MEMORY DEVICE AND A METHOD OF PROTECTING DATA THEREIN 有权
    一种安全的非易失性存储设备和一种保护数据的方法

    公开(公告)号：EP2074628A2

    公开(公告)日：2009-07-01

    申请号：EP07826558.4

    申请日：2007-09-27

    申请人： NXP B.V.

    发明人： TAO, Guoqiao

    IPC分类号： G11C16/22

    CPC分类号： G11C16/22 ,  G06F12/1408 ,  G06F21/72 ,  G06F21/79 ,  G11C11/005

    摘要： The invention relates to a non- volatile memory device comprising: an input for providing external data (D) to be stored on the non- volatile memory device; a first non- volatile memory block (100) and a second non- volatile memory block (200), the first non-volatile memory block (100) and the second non-volatile memory block (200) being provided on a single die (10), wherein the first non- volatile memory block (100) and second non- volatile memory block (200) are of a different type such that the first non-volatile memory block (100) and the second non-volatile memory block (200) require incompatible external attack techniques in order to retrieve data there from; and - an encryption circuit (50) for encrypting the external data (D) forming encrypted data (D', D') using unique data (K, Kl, K2) from at least the first non-volatile memory block (100) as an encryption key, the encrypted data (D', D') at least being stored into the second non-volatile memory block (200). The invention further relates to method of protecting data in a non- volatile memory device.

    摘要翻译： 本发明涉及一种非易失性存储器设备，包括：用于提供待存储在非易失性存储器设备上的外部数据（D）的输入端; 第一非易失性存储器块（100）和第二非易失性存储器块（200），所述第一非易失性存储器块（100）和所述第二非易失性存储器块（200）被设置在单个管芯 其中所述第一非易失性存储器块（100）和所述第二非易失性存储器块（200）是不同类型的，使得所述第一非易失性存储器块（100）和所述第二非易失性存储器块（100） 200）需要不兼容的外部攻击技术才能从中检索数据; 以及 - 加密电路（50），用于使用来自至少第一非易失性存储块（100）的唯一数据（K，K1，K2）将形成加密数据（D'，D'）的外部数据（D） 加密密钥，加密数据（D'，D'）至少被存储到第二非易失性存储器块（200）中。 本发明还涉及保护非易失性存储器设备中的数据的方法。