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    Semiconductor integrated circuit
    1.
    发明公开
    Semiconductor integrated circuit 失效
    半导体集成电路

    公开(公告)号：EP0614280A1

    公开(公告)日：1994-09-07

    申请号：EP94103119.7

    申请日：1994-03-02

    申请人： NEC CORPORATION

    发明人： Nakamura, Satoshi, c/o NEC Corporation

    IPC分类号： H03K19/013

    CPC分类号： H03K19/0136

    摘要： In the present invention, a PNP bipolar transistor (Q11) is connected to both ends of a resistive element (R11) of a SPL circuit so as to place an emitter thereof at the side of a power supply source (1). Resistive elements (R2,R4) and an NPN bipolar transistor (Q3) constitutes a bias circuit for biasing a low voltage to a base of the PNP bipolar transistor. The base of the PNP transistor (Q11) is connected to an emitter node of a NPN bipolar transistor (Q1) through a capacitative load element (C1). By this construction, the present invention can operate the signal without any delay to turn on the PNP bipolar transistor. Therefore, the collector response speed of the SPL circuit can be increased.

    摘要翻译： 在本发明中，PNP双极晶体管（Q11）连接到SPL电路的电阻元件（R11）的两端，以便将其发射极置于电源（1）侧。 电阻元件（R2，R4）和NPN双极晶体管（Q3）构成用于将低电压偏置到PNP双极晶体管的基极的偏置电路。 PNP晶体管（Q11）的基极通过电容负载元件（C1）连接到NPN双极晶体管（Q1）的发射极节点。 通过这种结构，本发明可以在没有任何延迟的情况下操作信号来导通PNP双极晶体管。 因此，可以增加SPL电路的集电极响应速度。

    Oversampling clock recovery having a high follow-up character using a few clock signals
    2.
    发明公开
    Oversampling clock recovery having a high follow-up character using a few clock signals 有权
    Taktrückgewinnungmit schneller Nachzieheigenschaft unter Verwendung weniger Taktsignale

    公开(公告)号：EP1223704A2

    公开(公告)日：2002-07-17

    申请号：EP02290070.8

    申请日：2002-01-11

    申请人： NEC CORPORATION

    发明人： Nakamura, Satoshi, c/o NEC Corporation

    IPC分类号： H04L7/033 ,  H03L7/081

    CPC分类号： H03L7/091 ,  H03L7/07 ,  H03L7/0814 ,  H03L7/087 ,  H03L7/0995 ,  H04L7/0337

    摘要： An oversampling clock recovery method according to this invention generates non-uniform three-phase clock signals CLKa, CLKb, and CLKc having non-uniform intervals for one bit of an input data i and controls phases of the clock signals so that either phase of two edges of two-phase clock signals CLKb and CLKc having a relatively narrower interval of 57ps synchronizes with a phase of a transition point of the input data i. By changing clock signals to be phase-locked in three delay locked loops (DLLs), a phase interval of 57ps is formed.

    摘要翻译： 根据本发明的过采样时钟恢复方法产生对输入数据i的一位具有不均匀间隔的不均匀三相时钟信号CLKa，CLKb和CLKc，并且控制时钟信号的相位，使得两相 具有57ps的较窄间隔的两相时钟信号CLKb和CLKc的边沿与输入数据i的转变点的相位同步。 通过在三个延迟锁定环（DLL）中改变要锁相的时钟信号，形成57ps的相位间隔。

    Clock recovery circuit and phase detecting method therefor
    3.
    发明公开
    Clock recovery circuit and phase detecting method therefor 有权
    Taktrückgewinnungsschaltungund Verfahren zur Phasendetektion

    公开(公告)号：EP1061651A1

    公开(公告)日：2000-12-20

    申请号：EP00112791.9

    申请日：2000-06-16

    申请人： NEC CORPORATION

    发明人： Nakamura, Satoshi, c/o NEC Corporation

    IPC分类号： H03L7/085 ,  H04L7/033

    CPC分类号： H03L7/0891 ,  H03L7/087 ,  H04L7/033

    摘要： A clock recovery circuit, which can recover a clock signal in high speed and can improve its jitter characteristic at the synchronized state, is provided. The clock recovery circuit provides a voltage controlled oscillator (VCO) which generates a reference clock signal CLK 1 whose frequency is about 1/2 Hz of inputted serial random data, a clock pulse CLK 2A whose phase lags by π/2 for the CLK 1, and a clock pulse CLK 2B whose phase leads by π/2 for the CLK 1, an edge detecting circuit for detecting positions of edges of the inputted serial random data, an detected edge selecting circuit for selecting whether the edges of the inputted serial random data are compared with rising edges or falling edges of the reference clock signal CLK 1, an edge position correcting circuit for comparing edges which corrects so that the number of the selected edges is made to be equal to the number of the edges of the inputted serial random data whose phases are compared by using the reference clock signal, and also corrects the positions of the edges of the inputted serial random data to positions to be compared their phases, phase frequency detectors which output pulses of the pulse width in proportion to the phase difference between the inputted serial random data and the reference clock signal.

    摘要翻译： 提供了一种时钟恢复电路，其可以高速恢复时钟信号并且可以在同步状态下提高其抖动特性。 时钟恢复电路提供压控振荡器（VCO），其产生频率为输入的串行随机数据的约1/2 Hz的参考时钟信号CLK 1，时钟脉冲CLK 2A，CLK相位相对于CLK1为π/ 2 ，以及CLK1相位导通π/ 2的时钟脉冲CLK 2B，用于检测输入的串行随机数据的边沿位置的边缘检测电路，检测到的边沿选择电路，用于选择输入的串行随机的边缘 将数据与参考时钟信号CLK1的上升沿或下降沿进行比较，边缘位置校正电路用于比较校正的边缘，使得所选择的边缘的数量等于所输入的串行数据的边缘的数量 通过使用参考时钟信号比较相位的随机数据，并且还将输入的串行随机数据的边沿的位置校正到要比较它们的相位的位置，相位频率检测器 其输出与输入的串行随机数据和参考时钟信号之间的相位差成比例的脉冲宽度的脉冲。