利索-全球专利检索

  1. 登录
  2. 注册

搜索结果

2 条记录 (耗时 0.009 秒)

    Semiconductor integrated circuit with error detecting circuit
    1.
    发明授权
    Semiconductor integrated circuit with error detecting circuit 失效
    具有故障检测电路的半导体集成电路

    公开(公告)号：EP0833249B1

    公开(公告)日：2003-03-19

    申请号：EP97250288.4

    申请日：1997-09-25

    申请人： NEC CORPORATION

    发明人： Sasaki, Makoto, c/o NEC IC Microcomp. Sys., Ltd.

    IPC分类号： G06F11/10 ,  G11C29/00 ,  G01R31/3185

    CPC分类号： G06F11/1008 ,  G11C29/36 ,  G11C29/40

    摘要： An instruction code is stored to an instruction ROM (2) in advance and the instruction ROM (2) outputs an instruction code signal (105) corresponding to an address signal (104). A program counter (1) sequentially outputs and stores the address signal (104) in synchronization with a clock signal (101). An instruction register (5) temporarily stores and outputs the instruction code signal (105) in synchronization with the clock signal (101). A check code generating circuit (7) generates a check code signal (114) every cycle of the clock signal (101) in accordance with a signal outputted of the instruction register (5) and the address signal (104). Thereafter, a comparator (9) detects an error in operation of the instruction ROM (2) by comparing the check code signal (114) and a check data signal (106) corresponding to the instruction code and its address value.

    Semiconductor integrated circuit with error detecting circuit
    2.
    发明公开
    Semiconductor integrated circuit with error detecting circuit 失效
    Integrierte Halbleiterschaltung mit Fehlererkennungsschaltung

    公开(公告)号：EP0833249A1

    公开(公告)日：1998-04-01

    申请号：EP97250288.4

    申请日：1997-09-25

    申请人： NEC CORPORATION

    发明人： Sasaki, Makoto, c/o NEC IC Microcomp. Sys., Ltd.

    IPC分类号： G06F11/10 ,  G11C29/00 ,  G01R31/3185

    CPC分类号： G06F11/1008 ,  G11C29/36 ,  G11C29/40

    摘要： An instruction code is stored to an instruction ROM (2) in advance and the instruction ROM (2) outputs an instruction code signal (105) corresponding to an address signal (104). A program counter (1) sequentially outputs and stores the address signal (104) in synchronization with a clock signal (101). An instruction register (5) temporarily stores and outputs the instruction code signal (105) in synchronization with the clock signal (101). A check code generating circuit (7) generates a check code signal (114) every cycle of the clock signal (101) in accordance with a signal outputted of the instruction register (5) and the address signal (104). Thereafter, a comparator (9) detects an error in operation of the instruction ROM (2) by comparing the check code signal (114) and a check data signal (106) corresponding to the instruction code and its address value.

    摘要翻译： 指令代码预先存储在指令ROM（2）中，指令ROM（2）输出对应于地址信号（104）的指令代码信号（105）。 程序计数器（1）与时钟信号（101）同步地顺序输出并存储地址信号（104）。 指令寄存器（5）与时钟信号（101）同步地临时存储并输出指令代码信号（105）。 校验码产生电路（7）根据从指令寄存器（5）和地址信号（104）输出的信号，每周期的时钟信号（101）生成校验码信号（114）。 此后，比较器（9）通过比较校验码信号（114）和对应于指令代码及其地址值的校验数据信号（106）来检测指令ROM（2）的操作中的错误。