摘要:
A memory device of address multiplex type which can outputs read data in sequence at a high speed is disclosed. The memory device is featured by an output circuit which maintains a read output generated under both active states of a row address strobe signal and a column address strobe signal, when one of the row and column address strobe signals is still active thereby to enlarge an effective width of the read output.
摘要:
A memory device of address multiplex type which can outputs read data in sequence at a high speed is disclosed. The memory device is featured by an output circuit which maintains a read output generated under both active states of a row address strobe signal and a column address strobe signal, when one of the row and column address strobe signals is still active thereby to enlarge an effective width of the read output.
摘要:
An interference wave detection circuit includes an amplifier (1) for amplifying a received carrier wave in response to a control signal; an amplitude detector (2) for amplitude-detecting the output of the amplifier; the output of said amplitude detector (2) being connected to the amplifier (1) as the control signal so as to make the output level of the amplifier (1) substantially constant; level measuring means (3) for measuring the level of the output fluctuation of the amplitude detector (2); a comparator (4) for comparing the output level of the level measuring means (3) with a predetermined level (Vc) to provide a compared output as an interference wave detection signal to the output of the interference wave detection circuit; discriminating means (6) connected to the output of the amplifier (1) for judging whether the received carrier wave is modulated or not; and gate means (7)(8) responsive to the output of the discriminating means (6) for preventing the compared output from reaching the output of the interference wave detection circuit when the discriminating means (6) judges that the received carrier wave is modulated.