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    Tristate output circuit
    2.
    发明公开
    Tristate output circuit 有权
    三态，Ausgangsschaltung

    公开(公告)号：EP0920132A1

    公开(公告)日：1999-06-02

    申请号：EP98120752.5

    申请日：1998-11-02

    申请人： NIPPON PRECISION CIRCUITS INC.

    发明人： Tsukagoshi, Kunihiko c/o Nippon Precision Circuits ,  Miyabe, Satoru c/o Nippon Precision Circuits Inc. ,  Oyama, Kazuhisa c/o Nippon Precision Circuits Inc.

    IPC分类号： H03K19/003 ,  H03K19/094 ,  H03K19/00

    CPC分类号： H03K19/0013 ,  H03K19/00323 ,  H03K19/09429

    摘要： The drains of P- and N-channel MOS transistors 1 and 2 are connected to each other. An output terminal is formed at the node of the drains. Each of first and second amplifier stages 4 and 5 is configured by cascading an n number of CMOS inverters. The amplifier stages drive first and second last-stage CMOS inverters 6 and 7 to drive the P- and N-channel MOS transistors 1 and 2, respectively. A dummy CMOS inverter 8 is disposed so that the input is connected to the node of the second amplifier stage 5 and the second last-stage CMOS inverter 7. The load of the second amplifier stage 5 is equal to that of the first amplifier stage 4. The drivabilities of the CMOS inverters of the same stage in the first and second amplifier stages 4 and 5 are made equal to each other. According to this configuration, the number of CMOS inverters which must be checked in a process of adjusting the duty can be reduced.

    摘要翻译： P沟道和N沟道MOS晶体管1和2的漏极相互连接。 输出端子形成在排水管的节点处。 第一和第二放大器级4和5中的每一个通过级联n个CMOS反相器来配置。 放大器级驱动第一和第二后级CMOS反相器6和7，分别驱动P沟道MOS晶体管和N沟道MOS晶体管1和2。 虚设CMOS反相器8被布置成使得输入端连接到第二放大器级5和第二最后级CMOS反相器7的节点。第二放大器级5的负载等于第一放大器级4的负载 使第一和第二放大器级4和5中相同级的CMOS反相器的驱动能力彼此相等。 根据该结构，可以减少在调整占空比的过程中必须检查的CMOS反相器的数量。