利索-全球专利检索

  1. 登录
  2. 注册

搜索结果

13 条记录 (耗时 0.017 秒)

    Echo canceler and echo path estimating method
    3.
    发明公开
    Echo canceler and echo path estimating method 失效
    回声消除器和回声路径估计方法

    公开(公告)号：EP1184998A2

    公开(公告)日：2002-03-06

    申请号：EP01127774.6

    申请日：1995-05-02

    申请人： NTT Mobile Communications Network Inc.

    发明人： Kawahara, Toshiro ,  Miki, Toshio ,  Suda, Hirohito ,  Ohya, Tomoyuki ,  Takagi, Hirofumi

    IPC分类号： H04B3/23

    CPC分类号： H04B3/238 ,  H04B3/23

    摘要： The present invention relates to an echo canceler for training an echo path estimation without providing a hindrance to a speech. The echo canceler of the present invention includes a pseudo noise generator for generating a certain pseudo noise. This pseudo noise is forcibly supplied to a transmission line for transmitting a far-end talker's voice. Here, in the case where the far-end talker's transmitting speech level is faint or the far-end talker is in a speechless condition, a certain correlation is established between the pseudo noise and a signal of the transmission line for transmitting the near-end talker's voice. Based on such a correlation as just mentioned, a coefficient for generating an echo replica is calculated. Therefore, a training for estimating an echo path is performed based on the pseudo noise and without depending on the far-end talker's voice, thereby enabling to generate an appropriate echo replica.

    摘要翻译： 本发明涉及用于训练回声路径估计而不会给语音造成障碍的回声消除器。 本发明的回波消除器包括用于产生特定伪噪声的伪噪声发生器。 该伪噪声被强制地提供给用于传输远端讲话者语音的传输线。 在此，在远端讲话者的发送话音电平微弱或者远端讲话者处于无声状态的情况下，在伪噪声和用于发送近端的传输线的信号之间建立一定的相关性 说话者的声音。 基于如上所述的这种相关性，计算用于生成回声复制品的系数。 因此，基于伪噪声并且不依赖于远端讲话者的语音来执行用于估计回声路径的训练，从而能够生成适当的回声复制品。

    Multi-stage interleaving device and method
    4.
    发明公开
    Multi-stage interleaving device and method 有权
    Vorrichtung und Verfahren zur mehrstufigen Verschachtelung

    公开(公告)号：EP1843474A1

    公开(公告)日：2007-10-10

    申请号：EP07014017.3

    申请日：1999-05-27

    申请人： NTT MOBILE COMMUNICATIONS NETWORK INC.

    发明人： Kawahara, Toshiro ,  Miki, Toshio ,  Hotani, Sanae ,  Suzuki, Takashi

    IPC分类号： H03M13/00 ,  H04L1/00 ,  H04N7/68

    CPC分类号： H04L1/0071 ,  H03M13/00 ,  H03M13/27 ,  H03M13/2703 ,  H03M13/2707 ,  H03M13/2764 ,  H03M13/2792 ,  H03M13/35 ,  H03M13/356 ,  H04L1/0009 ,  H04L1/0025 ,  H04L1/007 ,  H04L1/0072 ,  H04L1/0088

    摘要： The present invention relates to a multi-stage interleaving device, comprising N units of processing parts arranged in N stages from a bottom to a top, wherein N is an integer greater than 1. Each processing part comprises an operating memory configured to provide a matrix of storage areas having a width and a depth, a first input terminal configured to receive a first stream of bits and a second input terminal configured to receive a second stream of bits, a data writer configured to write the first stream of bits in storage areas in the matrix along the width from top left to bottom right and write the second stream of bits in successive storage areas in the matrix along the depth, a data reader configured to read the bits in the first and second streams from the matrix along the depth from top left to bottom right to output a third stream of bits in which the bits in the first stream are scattered into the second stream at intervals, and an output terminal configured to output the third stream of bits. Further, a plurality of connections serves for inputting and outputting streams of bits in and from the N processing parts.

    摘要翻译： 多级交织装置技术领域本发明涉及一种多级交织装置，包括从底部到顶部以N级布置的N个单位的处理部分，其中N是大于1的整数。每个处理部分包括操作存储器，其被配置为提供矩阵 具有宽度和深度的存储区域，被配置为接收第一比特流的第一输入端子和被配置为接收第二比特流的第二输入端子，被配置为将第一比特流写入存储区域中的数据写入器 沿着从左上到右下的宽度的矩阵中，沿所述深度在所述矩阵中的连续存储区域中写入所述第二比特流，数据读取器，被配置为沿着所述深度从所述矩阵读取所述第一和第二流中的比特 从左上角到右下角输出第三比特流，其中第一流中的比特以间隔被分散到第二个流中，并且输出终端被配置为输出t 奇怪的流。 此外，多个连接用于在N个处理部分中输入和输出比特流。

    Variable length coded data transmission device
    7.
    发明公开
    Variable length coded data transmission device 失效
    Vorrichtung zurÜbertragungvon mit variablerLängekodierten Daten

    公开(公告)号：EP0757493A2

    公开(公告)日：1997-02-05

    申请号：EP96111114.3

    申请日：1996-07-10

    申请人： NTT MOBILE COMMUNICATIONS NETWORK INC.

    发明人： Adachi, Satoru ,  Miki, Toshio ,  Ohya, Tomoyuki ,  Kawahara, Toshiro

    IPC分类号： H04N7/30

    CPC分类号： H04N21/236 ,  H04N7/56 ,  H04N21/434

    摘要： If a variable length code is caused to have a pseudo fixed length and transmitted in that condition, possible adverse effects due to out-of-synchronization attributable to code errors can be prevented, but it becomes difficult to enjoy this advantage in case an object to be fixed in length includes a block or blocks of variable length codes whose bit length is remarkably long. An object of the present invention is to obviate such a disadvantage as just mentioned. That is, for the transmission of variable length coded data blocks, a threshold arithmetic calculation circuit (9) obtains a threshold from an average of the bit lengths of the variable length coded data blocks for each group of such block., and the judgment circuit (10) makes a judgment as to whether or not those variable length coded data blocks have bit lengths exceeding the threshold of the block group to which such data blocks belong. Then, a block divider circuit 11 divides the variable length coded data blocks having bit lengths exceeding the threshold into blocks having small bit lengths. Each block thus obtained is fixedly equalized in bit length to an average length level and transmitted in that condition.

    摘要翻译： 如果使可变长度码具有伪固定长度并在该条件下发送，则可以防止由于代码错误引起的不同步造成的可能的不利影响，但是如果对象 固定长度包括位长非常长的可变长度代码块或块。 本发明的目的是消除如上所述的这样的缺点。 也就是说，对于可变长度编码数据块的传输，阈值算术运算电路（9）从每个这样的块组的可变长度编码数据块的比特长度的平均值中获得阈值，并且判断电路 （10）判断这些可变长度编码数据块是否具有超过这些数据块所属的块组的阈值的位长度。 然后，块分割器电路11将具有超过阈值的位长度的可变长度编码数据块划分为具有小位长度的块。 如此获得的每个块在位长度固定均衡到平均长度水平并在该条件下传输。

    Interleaving device and method with error protection
    8.
    发明公开
    Interleaving device and method with error protection 有权
    Verschachtelungsvorrichtung und Verfahren mit Fehlerschutz

    公开(公告)号：EP1841077A1

    公开(公告)日：2007-10-03

    申请号：EP07014011.6

    申请日：1999-05-27

    申请人： NTT MOBILE COMMUNICATIONS NETWORK INC.

    发明人： Kawahara, Toshiro ,  Miki, Toshio ,  Hotani, Sanae ,  Suzuki, Takashi

    IPC分类号： H03M13/27 ,  H03M13/35

    CPC分类号： H04L1/0071 ,  H03M13/00 ,  H03M13/27 ,  H03M13/2703 ,  H03M13/2707 ,  H03M13/2764 ,  H03M13/2792 ,  H03M13/35 ,  H03M13/356 ,  H04L1/0009 ,  H04L1/0025 ,  H04L1/007 ,  H04L1/0072 ,  H04L1/0088

    摘要： The present invention relates to an interleaving device with error protection, comprising a separator configured to divide at least one frame of data into categories of data according to error sensitivities of the data in the categories, an encoder configured to perform different types of error coding on the divided data to provide them with different error correction capacity, and an interleaver configured to rearrange the categories of data after encoding thereof so that a data category with higher error correction capacity is arranged at equal intervals in a data category with least error correction capacity.

    摘要翻译： 本发明涉及一种具有错误保护的交织装置，包括：分离器，被配置为根据类别中的数据的误差灵敏度将至少一帧数据划分成数据类别;编码器，被配置为执行不同类型的错误编码 分割数据以向它们提供不同的纠错能力，以及交织器，被配置为在编码之后重新排列数据类别，使得具有较高纠错能力的数据类别以相等的间隔排列在具有最小误差校正能力的数据类别中。

    Frame synchronization circuit and communications system
    10.
    发明公开
    Frame synchronization circuit and communications system 失效
    帧同步电路和通信系统

    公开(公告)号：EP0831616A3

    公开(公告)日：2000-04-05

    申请号：EP97115832.4

    申请日：1997-09-11

    申请人： NTT MOBILE COMMUNICATIONS NETWORK INC.

    发明人： Hotani, Sanae ,  Kawahara, Toshirou ,  Miki, Toshio

    IPC分类号： H04L7/04 ,  H04J3/06 ,  H04L1/00

    CPC分类号： H04L1/0047 ,  H04J3/0608 ,  H04L1/0007 ,  H04L1/0009 ,  H04L1/0046 ,  H04L1/0057 ,  H04L1/0061 ,  H04L7/048

    摘要： Likelihood calculating circuit A1 calculates the humming distance between a received data series and a unique word as likelihood data d1. Likelihood calculating circuit A2 calculates the number of transmission errors using redundant data, and outputs this value as likelihood data d2. Likelihood data d1,d2 are added at adding circuit 21, and the output thereof is compared to the threshold value of determination circuit with threshold 22. The results of this comparison are output as determination signal with threshold DT. Synchronous determination circuit 23 generates a synchronous determination signal SD based on determination signal with threshold DT. Accordingly, the present invention provides a frame synchronization circuit in which it is possible to avoid out of synchronization or false synchronization, without increasing the amount of redundancy necessary to detect frame synchronization.