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    FULLY PARALLEL TURBO DECODING
    8.
    发明公开
    FULLY PARALLEL TURBO DECODING 审中-公开
    完全平行的TURBO解码

    公开(公告)号：EP3180865A1

    公开(公告)日：2017-06-21

    申请号：EP15750665.0

    申请日：2015-07-30

    Applicant: Accelercomm Ltd

    Inventor： MAUNDER, Robert ,  LI, An ,  PEREZ-ANDRADE, Isaac

    IPC: H03M13/29 ,  H03M13/27

    CPC classification number: H03M13/1575 ,  H03M13/1111 ,  H03M13/2771 ,  H03M13/2789 ,  H03M13/2792 ,  H03M13/2957 ,  H03M13/3761 ,  H03M13/3769 ,  H03M13/45 ,  H03M13/617 ,  H03M13/6505 ,  H03M13/6513 ,  H03M13/6519 ,  H03M13/6525 ,  H03M13/6544 ,  H03M13/6561 ,  H04L1/0052 ,  H04L1/0055 ,  H04L1/0058 ,  H04L1/0071

    Abstract: A detection circuit performs a turbo detection process to recover a frame of data symbols from a received signal, the data symbols of the frame having been effected, during transmission, by a Markov process with the effect that the data symbols of the frame in the received signal are dependent one or more preceding data symbols which can be represented as a trellis having a plurality of trellis stages. The detection circuit comprises a plurality of processing elements, each of the processing elements is associated with one of the trellis stages representing the dependency of the data symbols of the frame according to the Markov process and each of the processing elements is configured to receive one or more soft decision values corresponding to one or more data symbols associated with the trellis stage, and each of one or more of the processing elements is configured, in one clock cycle to receive fixed point data representing a priori forward state metrics a priori backward state metrics, and fixed point data representing a priori soft decision values for the one or more data symbols being detected for the trellis stage. For each of a plurality of clock cycles of the turbo detection process, the detection circuit is configured to process, for each of the processing elements representing the trellis stages, the a priori information for the one or more data symbols being detected for the trellis stage associated with the processing element, and to provide the extrinsic soft decision values corresponding to the one or more data symbols for a next clock cycle of the turbo detection process.

    Abstract translation: 检测电路执行加速检测过程以通过马尔可夫过程从接收到的信号中恢复出一个数据符号帧，该马尔可夫过程的效果是接收信号中的符号取决于一个或多个先前的符号，该符号可以是 表示为具有多个阶段的格子。 检测电路包括多个处理元件706,708，每个元件与格栅级之一相关联。 每个元素接收对应于与格构级相关联的符号的软决策值，并且每个处理元件被配置为在一个时钟周期中接收表示先验正向平板度量的定点数据，先验反向状态度量和先验 网格阶段符号的软判决值。 对于每个周期，电路针对每个处理元件处理针对与处理元件相关联的级所检测到的符号的先验信息，并且t提供与检测处理的下一个时钟周期的符号相对应的非本征软判决值 。

    COMPUTATIONALLY EFFICIENT CONVOLUTIONAL CODING WITH RATE-MATCHING
    9.
    发明公开
    COMPUTATIONALLY EFFICIENT CONVOLUTIONAL CODING WITH RATE-MATCHING 审中-公开
    速率匹配的复数有效卷积编码

    公开(公告)号：EP3179655A1

    公开(公告)日：2017-06-14

    申请号：EP16198860.5

    申请日：2008-06-06

    Applicant: Telefonaktiebolaget LM Ericsson (publ)

    Inventor： Cheng, Jung-Fu

    IPC: H04L1/00 ,  H03M13/23

    CPC classification number: H03M13/2732 ,  H03M13/005 ,  H03M13/23 ,  H03M13/235 ,  H03M13/27 ,  H03M13/2792 ,  H03M13/2957 ,  H03M13/6356 ,  H03M13/6362 ,  H04L1/0059 ,  H04L1/0069 ,  H04L1/0071

    Abstract: An error coding circuit comprises a non-systematic convolutional encoder for coding an input bit stream to produce two or more groups of parity bits, an interleaver circuit for interleaving parity bits within each group of parity bits, wherein the interleaver circuit is configured to order parity bits such that odd parity bits precede even parity bits within each group of parity bits and a rate-matching circuit for outputting a selected number of the interleaved parity bits ordered by group to obtain a desired code rate.

    Abstract translation: 一种差错编码电路包括：非系统卷积编码器，用于对输入比特流进行编码以产生两组或更多组奇偶比特;交织器电路，用于交织每组奇偶比特中的奇偶比特，其中交织器电路被配置为命令奇偶校验 比特，使得奇校验比特在每组奇偶校验比特中的偶校验比特之前;以及速率匹配电路，用于输出按组排序的选定数目的交错校验比特以获得期望的码率。

    DECODING METHOD, DECODING APPARATUS, AND COMMUNICATIONS SYSTEM
    10.
    发明授权
    DECODING METHOD, DECODING APPARATUS, AND COMMUNICATIONS SYSTEM 有权
    解码方法，解码装置和通信系统

    公开(公告)号：EP2963830B1

    公开(公告)日：2017-06-14

    申请号：EP13881405.8

    申请日：2013-04-03

    Applicant: Huawei Technologies Co., Ltd.

    Inventor： YU, Fan ,  CHANG, Deyuan

    IPC: H04L1/00 ,  H04L27/06 ,  H03M13/11 ,  H03M13/29

    CPC classification number: H03M13/2792 ,  H03M13/1111 ,  H03M13/2957 ,  H03M13/3784 ,  H03M13/45 ,  H04L1/0045 ,  H04L1/005 ,  H04L1/007 ,  H04L27/06

    Abstract: The present invention provides a decoding method, a decoding apparatus, and a communications system, which implement multi-level coding in a manner combining soft-decision error correction coding and hard-decision error correction coding, implement multi-level decoding in a manner combining soft-decision error correction decoding and hard-decision error correction decoding, so as to integrate advantages of the two manners: compared with a manner in which soft-decision error correction coding and decoding are performed on multiple levels, a manner in which soft-decision error correction coding and decoding are performed on only one level reduces system complexity and resource overhead; and performing hard-decision error correction coding and decoding on other levels on a basis of performing soft-decision error correction coding and decoding on one level ensures gain performance, thereby meeting a gain requirement of a high-speed optical transmission system.

    Abstract translation: 本发明提供了一种解码方法，解码装置和通信系统，它们以组合软判决纠错编码和硬判决纠错编码的方式实现多级编码，以组合方式实现多级解码 软判决纠错译码和硬判决纠错译码，以便综合两种方式的优点：与在多个层次上进行软判决纠错编码和译码的方式相比， 仅在一个级别上执行判决纠错编码和解码，降低了系统复杂度和资源开销; 并在一级进行软判决纠错编解码的基础上，对其他各级进行硬判决纠错编码和解码，保证了增益性能，满足高速光传输系统的增益要求。

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