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    INTERLEAVING / DEINTERLEAVING DEVICE AND METHOD FOR COMMUNICATION SYSTEM
    1.
    发明公开
    INTERLEAVING / DEINTERLEAVING DEVICE AND METHOD FOR COMMUNICATION SYSTEM 审中-公开
    交织/去交织设备和通信系统的方法

    公开(公告)号：EP3226423A1

    公开(公告)日：2017-10-04

    申请号：EP17157428.8

    申请日：1999-12-27

    Applicant: Samsung Electronics Co., Ltd.

    Inventor： KIM, Min-Goo ,  KIM,, Beong-Jo ,  LEE,, Young-Hwan

    IPC: H03M13/27

    CPC classification number: H04L1/0066 ,  H03M13/271 ,  H03M13/2764 ,  H03M13/2771 ,  H03M13/2789 ,  H04L1/005 ,  H04L1/0071

    Abstract: An interleaving method comprises storing input data in a memory according to a sequential address; providing a virtual address determined by adding an predetermined value to a size of the input data so that a partial bit reversal ordering interleaving rule is satisfied; matching the virtual address to an address interleaved according to the interleaving rule; and reading the input data from the memory using an address other than the address corresponding to the specific value, out of the interleaved addresses.

    Abstract translation: 一种交织方法包括：根据顺序地址将输入数据存储在存储器中; 提供通过将预定值与输入数据的大小相加而确定的虚拟地址，从而满足部分比特反转排序交织规则; 将虚拟地址匹配到根据交织规则交织的地址; 以及使用除了与特定值对应的地址之外的地址从交织地址中读取来自存储器的输入数据。

    Data processing apparatus and method
    2.
    发明公开
    Data processing apparatus and method 审中-公开
    数据处理装置和方法

    公开(公告)号：EP2129067A3

    公开(公告)日：2015-12-30

    申请号：EP09251245.8

    申请日：2009-05-01

    Applicant: Sony Corporation

    Inventor： Samuel Asambeng Atungsiri ,  Matthew Paul Athol Taylor

    IPC: H04L27/26 ,  H03M13/27 ,  H04L1/00 ,  H04N5/44

    CPC classification number: H04L27/2602 ,  H03M13/2742 ,  H03M13/2764 ,  H04L1/0071 ,  H04L27/2647 ,  H04N21/6112

    Abstract: A data processing apparatus is operable to map data symbols received from sub-carrier signals of Orthogonal Frequency Division Multiplexed (OFDM) symbols into an output data stream. The data processing apparatus includes an address generator, an interleaver memory and a controller. The controller is operable, when operating in accordance with an even interleaving process to read out from the interleaver memory a first set of the data symbols into the output data stream using addresses generated by the address generator, to write into the interleaver memory a second set of the data symbols received from the sub-carrier signals of an even OFDM symbol using the addresses generated by the address generator. The controller is operable in accordance with an odd interleaving process, to read out from the interleaver memory a first set of the data symbols into the output data stream using read addresses determined in accordance with a sequential order of the first set of data symbols, and to write into the interleaver memory a second set of the data symbols received from the sub-carrier signals of an odd OFDM symbol at write addresses determined in accordance with a sequential order of the first set of input data symbols, such that while data symbols from the first set are being read from locations in the interleaver memory, input data symbols from the second set can be written to the locations just read from. The number of the sub-carriers which are available from a previous OFDM symbol is different from the number of the sub-carriers which are available from a current OFDM symbol, and the controller is operable to determine before reading out the first data symbols from the interleaver memory, whether the read address is valid for the previous OFDM symbol, and to determine before writing the second data symbols into the interleaver memory, whether the write address is valid for the current OFDM symbol. Application can be found with DVB Cable 2, which can provide substantially four thousand carriers.

    Abstract translation: 数据处理装置可操作用于将从正交频分复用（OFDM）符号的副载波信号接收到的数据符号映射到输出数据流中。 数据处理装置包括地址生成器，交织器存储器和控制器。 当根据偶数交错过程操作以使用地址生成器生成的地址将第一组数据符号从交织器存储器读出到输出数据流中时，控制器可操作以将第二组 使用由地址生成器生成的地址从偶数OFDM符号的子载波信号接收的数据符号。 控制器可根据奇数交错过程操作，以使用根据第一组数据符号的顺序确定的读取地址从交织器存储器读出第一组数据符号到输出数据流中，以及 在根据第一组输入数据符号的顺序确定的写入地址处将从奇数OFDM符号的副载波信号接收到的第二组数据符号写入交织器存储器，使得当来自 第一组从交织器存储器中的位置被读取，来自第二组的输入数据符号可被写入刚读取的位置。 从先前的OFDM符号可获得的子载波的数目不同于可从当前OFDM符号获得的子载波的数目，并且控制器可操作以在从第一OFDM符号读出第一数据符号之前 交织器存储器确定读取地址对于前一个OFDM符号是否有效，并且在将第二数据符号写入交织器存储器之前确定写入地址对于当前OFDM符号是否有效。 应用程序可以在DVB Cable 2中找到，它可以提供大约四千个载波。

    Dat processing apparatus and method
    3.
    发明公开
    Dat processing apparatus and method 有权
    Dat处理装置和方法

    公开(公告)号：EP2129066A3

    公开(公告)日：2015-12-30

    申请号：EP09251244.1

    申请日：2009-05-01

    Applicant: Sony Corporation

    Inventor： Atungsiri, Samuel Asanbeng ,  Taylor, Matthew Paul Athol

    IPC: H04L27/26 ,  H03M13/27 ,  H04L1/00 ,  H04N5/44

    CPC classification number: H04L27/2602 ,  H03M13/2742 ,  H03M13/2764 ,  H04L1/0071 ,  H04L27/2647 ,  H04N21/6112

    Abstract: A data processing apparatus is operable to map input data symbols to be communicated onto a predetermined number of sub-carrier signals of Orthogonal Frequency Division Multiplexed OFDM symbols. The predetermined number of sub-carrier signals is determined in accordance with one of a plurality of operating modes and the input data symbols include first sets of data symbols and second sets of input data symbols. The data processing apparatus includes a controller, an address generator and an interleaver memory. The controller is operable, when operating in accordance with an even interleaving process to read out a first set of the input data symbols from the interleaver memory on to the sub-carrier signals of an even OFDM symbol using read addresses generated by the address generator, and to write in a second set of the input data symbols into the interleaver memory using the addresses generated by the address generator. The controller is operable in accordance with an odd interleaving process, to read out a first set of input data symbols from the interleaver memory on to the sub-carrier signals of an odd OFDM symbol using read addresses determined in accordance with a sequential order of the first set of input data symbols, and to write in a second set of the input data symbols into the interleaver memory at write addresses determined in accordance with the sequential order of the first group of input data symbols. The controller is operable to determine before reading out the first input data symbols from the interleaver memory, whether the read address is valid for a previous OFDM symbol, and to determine before writing the second input data symbols into the interleaver memory, whether the write address is valid for a current OFDM symbol. As such, the interleaver memory size can be minimised to an amount which corresponds to a maximum number of sub-carriers, which are available for an OFDM symbol for any of the operating modes. Application can be found with DVB-T2, which includes a 32K mode.

    Abstract translation: 数据处理装置可操作用于将要传送的输入数据符号映射到正交频分复用OFDM符号的预定数量的子载波信号上。 预定数量的副载波信号根据多个操作模式中的一个来确定，并且输入数据符号包括第一组数据符号和第二组输入数据符号。 该数据处理装置包括控制器，地址生成器和交织器存储器。 当根据偶数交织过程操作以使用由地址生成器生成的读地址从交织器存储器读出第一组输入数据码元到偶数OFDM码元的子载波信号时，控制器可操作， 并使用由地址生成器生成的地址将第二组输入数据符号写入交织器存储器。 控制器可根据奇数交错过程进行操作，以使用根据第一组输入数据符号的序列次序确定的读取地址从交织器存储器中读出第一组输入数据符号到奇数OFDM符号的子载波信号上 第一组输入数据符号，并且在按照第一组输入数据符号的顺序次序确定的写入地址处将第二组输入数据符号写入交织器存储器。 控制器可操作以在从交织器存储器读出第一输入数据码元之前确定读取地址对于先前OFDM码元是否有效，并且在将第二输入数据码元写入交织器存储器之前确定写入地址 对当前的OFDM符号有效。 如此，交织器存储器大小可被最小化到与可用于任何操作模式的OFDM符号的最大数量的子载波对应的量。 应用程序可以在包含32K模式的DVB-T2中找到。

    Communication methods and systems having permutation schemes
    4.
    发明公开
    Communication methods and systems having permutation schemes 审中-公开
    沟通的方法和系统Permutationschemen

    公开(公告)号：EP2182664A3

    公开(公告)日：2015-10-07

    申请号：EP09174486.2

    申请日：2009-10-29

    Applicant: Industrial Technology Research Institute

    Inventor： Tsai, Chia-Lung ,  Hsieh, Yu-Tao ,  Hsu, Jen-Yuan ,  Ting, Pang-An

    IPC: H04L1/00 ,  H03M13/27

    CPC classification number: H04L1/0071 ,  H03M13/275 ,  H03M13/2764 ,  H03M13/6544 ,  H04L1/0065 ,  H04L1/04

    Abstract: A wireless communication method implemented in a communication system includes receiving a first data sequence, and processing the first data sequence to obtain information containing at least one of a first number and a sampling spacing associated with the first data sequence. The method also includes permuting the first data sequence to generate a permuted second data sequence. Permuting the first data sequence includes determining a first parameter based on at least one of the first number and the sampling spacing, determining a second parameter based on at least one of the first parameter, the first number, and the sampling spacing, and determining a mapping relationship between a j-th data item of the permuted second data sequence and an i-th data item of the first data sequence. The method further includes outputting the permuted second data sequence.

    Data transmission with interleaving through in-place addressing of RAM memory
    8.
    发明公开
    Data transmission with interleaving through in-place addressing of RAM memory 失效
    通过就地寻址RAM存储器交错数据传输

    公开(公告)号：EP1635473A3

    公开(公告)日：2009-02-25

    申请号：EP05110955.1

    申请日：1996-01-26

    Applicant: Sony Corporation

    Inventor： Baggen, Constant, P., M., J.

    IPC: H03M13/27

    CPC classification number: H03M13/2785 ,  H03M13/275 ,  H03M13/2764 ,  H04L1/0071 ,  H04L27/2602

    Abstract: Data is transmitted with a signal containing a number of simultaneously active OFDM modulated frequency channels. The data may be encoded in an error protecting code. Successive data items are mapped pseudo-randomly to different frequency channels. This protects against fading which affects frequency channels that are located at periodic distances from each other. The pseudo random mapping is realized by writing the data-items into memory in one order and reading them from memory in another order. Successive signals are each modulated in this way. The memory locations vacated upon reading for the modulation of one signal are filled by data-items for modulating the next successive signal. This is kept up by permuting the order of the memory locations in which the data-items are written for each successive signal.

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