公开(公告)号：EP2351232B1

公开(公告)日：2017-01-11

申请号：EP09760000.1

申请日：2009-11-12

Applicant: NXP B.V.

Inventor： DORIS, Konstantinos ,  JANSSEN, Erwin

IPC: H04B1/00 ,  H03H17/02 ,  H04N5/44

CPC classification number: H04B1/001 ,  H03H17/06 ,  H03H2218/08 ,  H04B1/0025

公开(公告)号：EP2347509B1

公开(公告)日：2012-12-12

申请号：EP09740964.3

申请日：2009-10-05

Applicant: NXP B.V.

Inventor： DORIS, Konstantinos ,  JANSSEN, Erwin

IPC: H03M1/06 ,  H03M1/46

CPC classification number: H03M1/0614 ,  H03M1/1215 ,  H03M1/466

公开(公告)号：EP3484053A1

公开(公告)日：2019-05-15

申请号：EP17201605.7

申请日：2017-11-14

Applicant: NXP B.V.

Inventor： LIN, Yu ,  JANSSEN, Erwin ,  DYACHENKO, Vladislav

IPC: H03M1/18 ,  H03M1/46

Abstract: A successive approximation register, SAR, analog-to-digital converter, ADC, (400) is described. The SAR ADC (400) includes: an analog input signal (410); an ADC core (414) configured to receive the analog input signal (410) and comprising: a digital to analog converter, DAC (430) located in a feedback path; and a SAR controller (418) configured to control an operation of the DAC (430), wherein the DAC (430) comprises a number of DAC cells, arranged to convert a digital code from the SAR controller (418) to an analog form; a digital signal reconstruction circuit (450) configured to convert the digital codes from the SAR controller (418) to a binary form; and an output coupled to the digital signal reconstruction circuit (450) and configured to provide a digital data output (460). The DAC (430) is configurable to support at least two mapping modes, including a small signal mapping mode of operation; and the SAR controller (418) is configured to identify when the received analog signal is a small signal level, and in response thereto re-configure the DAC (430) and the digital signal reconstruction circuit (450) to implement a small signal mapping mode of operation.

公开(公告)号：EP3477864A1

公开(公告)日：2019-05-01

申请号：EP17199331.4

申请日：2017-10-31

Applicant: NXP B.V.

Inventor： VAUCHER, Cicero Silveira ,  JANSSEN, Erwin ,  DERKSEN, Sander ,  KUP, Bernardus Martinus

IPC: H03L7/18

Abstract: There is disclosed an apparatus comprising a first phase-locked loop comprising: a phase detector (302, 304), arranged to receive a reference clock signal (306) and a feedback clock signal (308) and to output a frequency control signal based on a phase difference between the reference clock signal (306) and the feedback clock signal (308); a variable-frequency oscillator (312, 314) arranged to output an oscillator signal having a frequency dependent on said frequency control signal; first divider circuitry (316) for generating said feedback clock signal (308) by frequency-dividing said oscillator signal; and second divider circuitry (320) for generating an output clock signal (3220 by frequency-dividing said oscillator signal; wherein a phase relation between said first divider circuitry (316) and said second divider circuitry (320) is adjustable to delay or advance said output clock signal (322) relative to said feedback clock signal (308). The apparatus may be a radar receiver or transceiver.

公开(公告)号：EP2156549A2

公开(公告)日：2010-02-24

申请号：EP08763121.4

申请日：2008-05-27

Applicant: NXP B.V.

Inventor： JANSSEN, Erwin

IPC: H03D3/00

CPC classification number: H03D3/006 ,  H03H17/06 ,  H03H2017/0247 ,  H03H2218/04

Abstract: A digital signal processing circuit comprises a band selector (14) for selecting at least one sub-band from a frequency spectrum of a digital sampled input signal. The band selector (14) comprises a plurality of processing branches corresponding to respective phases and an adder (28a, 28b) for adding branch signals from the branches. Each branch comprises a sub-sampler (20a,b) for sub-sampling sample values of the input signal at the phase corresponding to the branch, a filter (24a,b) with a first FIR filter (32, 34), applied alternatingly to sets of even and to sets of odd samples from the subsampler (20a,b) and a second FIR filter (36, 38) applied to further sets of odd and even samples from the subsampler (20a,b) when the first FIR filter is applied to the even and odd sets respectively. Output samples from the first and second FIR filter (24a,b) are combined to form the branch signals of the branch, according to a changing combination pattern that changes cyclically as a function of sample position and depends on a phase for which the branch is used.

公开(公告)号：EP2092681A1

公开(公告)日：2009-08-26

申请号：EP07849274.1

申请日：2007-11-28

Applicant: NXP B.V.

Inventor： BESTEN, Gerrit ,  JANSSEN, Erwin

IPC: H04L7/033 ,  H04L7/10 ,  H03L7/08

CPC classification number: H04L7/10 ,  H03L7/0991 ,  H03L2207/50 ,  H04L7/0331

Abstract: The invention relates to a circuit and method for receiving a signal of which - at the receiver end - the frequency is basically unknown. By sampling the data and deriving the frequency of the signal (or actually: the data rate of the data carried by the signal) and setting a phase locked loop in the receiver to the derived - est imated - circuit, the receiver can very quickly tune in to the frequency of the signal. Hence, no embedded or accompanying clock is required for the signal. Oversampling of the signal by the receiver front end is preferred, though.

公开(公告)号：EP3477864B1

公开(公告)日：2020-07-08

申请号：EP17199331.4

申请日：2017-10-31

Applicant: NXP B.V.

Inventor： VAUCHER, Cicero Silveira ,  JANSSEN, Erwin ,  DERKSEN, Sander ,  KUP, Bernardus Martinus

IPC: H03L7/18

公开(公告)号：EP2347509A1

公开(公告)日：2011-07-27

申请号：EP09740964.3

申请日：2009-10-05

Applicant: NXP B.V.

Inventor： DORIS, Konstantinos ,  JANSSEN, Erwin

IPC: H03M1/06 ,  H03M1/46

CPC classification number: H03M1/0614 ,  H03M1/1215 ,  H03M1/466

Abstract: This invention relates to Analog to Digital Converters (ADC) and, inter alia, to Time Interleaved ADCs and Successive Approximation Register (SAR) ADC's. In a conventional Time Interleaved ADC employing SAR ADC units, the input signal is processed through a track-and-hold circuit (T/H), and then through a buffer circuit, before the SAR ADC unit. There, by means of a comparator, the signal is compared with a Digital-to-Analog Converter (DAC) signal from the SAR logic. The buffer reduces the influence of capacitive loading and physical layout design on the SAR ADC input, but typically has a non-linear response and thus introduces distortion to the input signal. This can limit the ADC linearity, particularly for high-speed ADCs operating with low-supply voltages. An objective of the invention is to reduce or eliminate the effect of the buffer non-linearity. This is done in some embodiments by routing both the signals to the comparator through the same buffer circuit. In another embodiment the DAC signal is routed through a separate second buffer circuit. By use of a single buffer circuit, or where there is ideal matching of the buffer circuits in the latter embodiment, the distortion effects are completely eliminated; however, for practical imperfectly matched buffer circuits according to the latter embodiment, the gain and off-set mismatches can be accommodated through calibration of the buffers or, in suitable applications, through the DAC calibration.

Abstract translation: 本发明涉及模数转换器（ADC），尤其涉及时间交错ADC和逐次逼近寄存器（SAR）ADC。 在采用SAR ADC单元的传统时间交错ADC中，输入信号在SAR ADC单元之前通过采样保持电路（T / H），然后通过缓冲电路进行处理。 在那里，通过比较器将信号与来自SAR逻辑的数字 - 模拟转换器（DAC）信号进行比较。 该缓冲器降低了电容性负载和物理布局设计对SAR ADC输入的影响，但通常具有非线性响应，因此会在输入信号中引入失真。 这可能会限制ADC线性度，特别是对于使用低电源电压工作的高速ADC。 本发明的目的是减少或消除缓冲非线性的影响。 这在一些实施例中通过将两个信号通过相同的缓冲器电路路由到比较器来完成。 在另一个实施例中，DAC信号被路由通过单独的第二缓冲器电路。 通过使用单个缓冲电路，或者在后面的实施例中存在缓冲电路的理想匹配的情况下，失真效应被完全消除; 然而，对于根据后一实施例的实际不完全匹配的缓冲器电路，增益和偏移失配可以通过缓冲器的校准或在合适的应用中通过DAC校准来适应。

公开(公告)号：EP2092681B1

公开(公告)日：2011-04-13

申请号：EP07849274.1

申请日：2007-11-28

Applicant: NXP B.V.

Inventor： BESTEN, Gerrit ,  JANSSEN, Erwin

IPC: H04L7/033 ,  H04L7/10 ,  H03L7/08

CPC classification number: H04L7/10 ,  H03L7/0991 ,  H03L2207/50 ,  H04L7/0331

Abstract: The invention relates to a circuit and method for receiving a signal of which - at the receiver end - the frequency is basically unknown. By sampling the data and deriving the frequency of the signal (or actually: the data rate of the data carried by the signal) and setting a phase locked loop in the receiver to the derived - est imated - circuit, the receiver can very quickly tune in to the frequency of the signal. Hence, no embedded or accompanying clock is required for the signal. Oversampling of the signal by the receiver front end is preferred, though.

公开(公告)号：EP2263318A2

公开(公告)日：2010-12-22

申请号：EP09723168.2

申请日：2009-03-17

Applicant: NXP B.V.

Inventor： VAN DER PLOEG, Hendrik ,  JANSSEN, Erwin ,  DORIS, Konstantinos

IPC: H03M1/36

CPC classification number: H03M1/361 ,  H03M1/34

Abstract: An analog-to-digital converter comprises a signal input (6) for receiving an analog input signal and a set of comparators (4). Each comparator (4) has a first input (21 ) connected to the signal input (6) and a second input (22) connected to a reference voltage (16). Each comparator generates an output based on the comparison of the signals at the first input (21 ) and second input (22). The reference voltage is the same for all comparators. The set of comparators (4) has a non-identical response to the reference voltage (16) and the input signal and is due to an internally arising offset. An adder (25) determines a sum of the outputs of the set of comparators and conversion logic (27) generates an output digital signal dependent on the determined sum. Multiple sets of comparators can be provided, each set having a different respective reference voltage.

Abstract translation: 模数转换器包括用于接收模拟输入信号的信号输入（6）和一组比较器（4）。 每个比较器（4）具有连接到信号输入端（6）的第一输入端（21）和连接到参考电压（16）的第二输入端（22）。 每个比较器基于第一输入（21）和第二输入（22）之间的信号的比较产生输出。 所有比较器的参考电压相同。 比较器（4）的集合对参考电压（16）和输入信号具有不相同的响应，并且是由于内部产生的偏移。 加法器（25）确定比较器组的输出的和，并且转换逻辑（27）根据确定的和产生输出数字信号。 可以提供多组比较器，每组具有不同的各自的参考电压。