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    ERROR PROCESSING IN TIME INTERLEAVED SIGNAL PROCESSING DEVICES
    3.
    发明授权
    ERROR PROCESSING IN TIME INTERLEAVED SIGNAL PROCESSING DEVICES 有权
    错误处理均与交错信号处理器件

    公开(公告)号：EP2156562B1

    公开(公告)日：2012-07-11

    申请号：EP08763118.0

    申请日：2008-05-27

    Applicant: NXP B.V.

    Inventor： DORIS, Konstantinos

    IPC: H03M1/06 ,  H03M1/12

    CPC classification number: H03M1/0678 ,  H03M1/066 ,  H03M1/1215

    Abstract: The present invention relates to a signal processing apparatus comprising a signal input and a signal output; a plurality of signal processing units, wherein each signal processing unit having the same structure and at least one spatial error, being connected to the signal input, and being adapted to subject an input signal from the signal input to predetermined signal processing; selection means configured to select and form a predetermined number of groups from the plurality of signal processing units in accordance with a predetermined criterion; and control means for controlling the groups of the signal processing units to be active in a time interleaved schema, wherein an active group provides a respective processed input -signal as an output signal to the signal output; wherein the plurality of signal processing units comprises more signal processing units as required to realize a predetermined time interleaving factor.

    AN ADC
    4.
    发明公开
    AN ADC 有权

    公开(公告)号：EP2347509A1

    公开(公告)日：2011-07-27

    申请号：EP09740964.3

    申请日：2009-10-05

    Applicant: NXP B.V.

    Inventor： DORIS, Konstantinos ,  JANSSEN, Erwin

    IPC: H03M1/06 ,  H03M1/46

    CPC classification number: H03M1/0614 ,  H03M1/1215 ,  H03M1/466

    Abstract: This invention relates to Analog to Digital Converters (ADC) and, inter alia, to Time Interleaved ADCs and Successive Approximation Register (SAR) ADC's. In a conventional Time Interleaved ADC employing SAR ADC units, the input signal is processed through a track-and-hold circuit (T/H), and then through a buffer circuit, before the SAR ADC unit. There, by means of a comparator, the signal is compared with a Digital-to-Analog Converter (DAC) signal from the SAR logic. The buffer reduces the influence of capacitive loading and physical layout design on the SAR ADC input, but typically has a non-linear response and thus introduces distortion to the input signal. This can limit the ADC linearity, particularly for high-speed ADCs operating with low-supply voltages. An objective of the invention is to reduce or eliminate the effect of the buffer non-linearity. This is done in some embodiments by routing both the signals to the comparator through the same buffer circuit. In another embodiment the DAC signal is routed through a separate second buffer circuit. By use of a single buffer circuit, or where there is ideal matching of the buffer circuits in the latter embodiment, the distortion effects are completely eliminated; however, for practical imperfectly matched buffer circuits according to the latter embodiment, the gain and off-set mismatches can be accommodated through calibration of the buffers or, in suitable applications, through the DAC calibration.

    Abstract translation: 本发明涉及模数转换器（ADC），尤其涉及时间交错ADC和逐次逼近寄存器（SAR）ADC。 在采用SAR ADC单元的传统时间交错ADC中，输入信号在SAR ADC单元之前通过采样保持电路（T / H），然后通过缓冲电路进行处理。 在那里，通过比较器将信号与来自SAR逻辑的数字 - 模拟转换器（DAC）信号进行比较。 该缓冲器降低了电容性负载和物理布局设计对SAR ADC输入的影响，但通常具有非线性响应，因此会在输入信号中引入失真。 这可能会限制ADC线性度，特别是对于使用低电源电压工作的高速ADC。 本发明的目的是减少或消除缓冲非线性的影响。 这在一些实施例中通过将两个信号通过相同的缓冲器电路路由到比较器来完成。 在另一个实施例中，DAC信号被路由通过单独的第二缓冲器电路。 通过使用单个缓冲电路，或者在后面的实施例中存在缓冲电路的理想匹配的情况下，失真效应被完全消除; 然而，对于根据后一实施例的实际不完全匹配的缓冲器电路，增益和偏移失配可以通过缓冲器的校准或在合适的应用中通过DAC校准来适应。

    FLASH ANALOG-TO-DIGITAL CONVERTER
    5.
    发明公开
    FLASH ANALOG-TO-DIGITAL CONVERTER 有权
    FLASH-模拟 - 数字 - WANDLER

    公开(公告)号：EP2263318A2

    公开(公告)日：2010-12-22

    申请号：EP09723168.2

    申请日：2009-03-17

    Applicant: NXP B.V.

    Inventor： VAN DER PLOEG, Hendrik ,  JANSSEN, Erwin ,  DORIS, Konstantinos

    IPC: H03M1/36

    CPC classification number: H03M1/361 ,  H03M1/34

    Abstract: An analog-to-digital converter comprises a signal input (6) for receiving an analog input signal and a set of comparators (4). Each comparator (4) has a first input (21 ) connected to the signal input (6) and a second input (22) connected to a reference voltage (16). Each comparator generates an output based on the comparison of the signals at the first input (21 ) and second input (22). The reference voltage is the same for all comparators. The set of comparators (4) has a non-identical response to the reference voltage (16) and the input signal and is due to an internally arising offset. An adder (25) determines a sum of the outputs of the set of comparators and conversion logic (27) generates an output digital signal dependent on the determined sum. Multiple sets of comparators can be provided, each set having a different respective reference voltage.

    Abstract translation: 模数转换器包括用于接收模拟输入信号的信号输入（6）和一组比较器（4）。 每个比较器（4）具有连接到信号输入端（6）的第一输入端（21）和连接到参考电压（16）的第二输入端（22）。 每个比较器基于第一输入（21）和第二输入（22）之间的信号的比较产生输出。 所有比较器的参考电压相同。 比较器（4）的集合对参考电压（16）和输入信号具有不相同的响应，并且是由于内部产生的偏移。 加法器（25）确定比较器组的输出的和，并且转换逻辑（27）根据确定的和产生输出数字信号。 可以提供多组比较器，每组具有不同的各自的参考电压。

    SYSTEMS AND METHODS FOR CALIBRATION OF IN-PHASE/QUADRATURE (I/Q) MODULATORS
    7.
    发明公开
    SYSTEMS AND METHODS FOR CALIBRATION OF IN-PHASE/QUADRATURE (I/Q) MODULATORS 审中-公开

    公开(公告)号：EP3993336A1

    公开(公告)日：2022-05-04

    申请号：EP21201192.8

    申请日：2021-10-06

    Applicant: NXP B.V.

    Inventor： NEOFYTOU, Marios ,  DORIS, Konstantinos ,  GANZERLI, Marcello ,  RADULOV, Georgi ,  ATHANASIADIS, Pavlos

    IPC: H04L27/36 ,  H04L27/00 ,  H04B1/04

    Abstract: A wireless transceiver system includes a transmitter and a receiver. The transmitter includes a digital processor and a self-correction modulator coupled to the digital processor, wherein based upon a calibration correction assessment of an in-phase (I) signal and a quadrature (Q) signal received from the digital processor, the self-correction modulator generates a calibrated modulated signal. The self-correction modulator includes a core modulator and a calibration correction unit. The calibration correction unit is configured to correct an output of the core modulator based upon the calibration correction assessment. The calibration correction unit includes a calibration processing unit and a calibration modulator, wherein the calibration processing unit provides correction quantities that are used to program the calibration modulator to provide the self-corrected modulated signal.

    SYSTEMS AND METHODS FOR PROCESSING ERRORS IN DIGITAL BEAMFORMING RECEIVERS
    8.
    发明公开
    SYSTEMS AND METHODS FOR PROCESSING ERRORS IN DIGITAL BEAMFORMING RECEIVERS 审中-公开

    公开(公告)号：EP3985877A1

    公开(公告)日：2022-04-20

    申请号：EP21200915.3

    申请日：2021-10-05

    Applicant: NXP B.V.

    Inventor： ATHANASIADIS, Pavlos ,  DORIS, Konstantinos ,  NEOFYTOU, Marios ,  RADULOV, Georgi

    IPC: H03M1/10 ,  H03M1/12

    Abstract: An apparatus, such as a radar system that conducts beamforming operations, includes a plurality of analog-to-digital-converters (ADCs) and an error correction system coupled to the ADCs. Based upon an assessment of a plurality of errors associated with the ADCs by the error correction system, the error correction system programs sampling operations for the ADCs. The error correction system includes an error correction unit that identifies the plurality of errors associated with a plurality of sub-ADCs of the ADCs, a selection unit coupled to the error correction unit that sorts the errors associated with the plurality of sub-ADCs, and a programming unit coupled to the selection unit that reconfigures the sorted errors to generate a sequence of sampling operations for the plurality of sub-ADCs. Using, for example, a barrel shifter function, the sorted errors are reconfigured by the programming unit such that a summation of elements in each column in a matrix in which the sorted errors are stored are within a predefined value.

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