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    SEMICONDUCTOR DEVICE MANUFACTURING METHOD
    1.
    发明公开
    SEMICONDUCTOR DEVICE MANUFACTURING METHOD 有权
    半导体器件制造方法

    公开(公告)号：EP1915773A1

    公开(公告)日：2008-04-30

    申请号：EP06767742.7

    申请日：2006-06-26

    申请人： Nissan Motor Company Limited

    发明人： YAMAGAMI, Shigeharu ,  HOSHI, Masakatsu ,  HAYASHI, Tetsuya ,  TANAKA, HIDEAKI ,  SHIMOIDA, Yoshio

    IPC分类号： H01L21/18 ,  H01L29/78 ,  H01L29/24 ,  H01L29/267

    CPC分类号： H01L29/1608 ,  H01L29/267 ,  H01L29/66068 ,  H01L29/7827

    摘要： A method of manufacturing a semiconductor device having a polycrystalline silicon layer (5) includes; a step of forming a mask layer (7) on the polycrystalline silicon layer (5); a step of forming a side wall (8) that is provided on a side face of the mask layer (7) and covers part of the polycrystalline silicon layer (6); a step of doping an impurity (52) into the polycrystalline silicon layer (5) by using at least one of the mask layer (7) and the side wall (8) as a mask; and a step of etching the polycrystalline silicon layer (5, 6) by using at least one of the mask layer (7) and the side wall (8) as a mask.

    摘要翻译： 一种制造具有多晶硅层（5）的半导体器件的方法包括： 在多晶硅层（5）上形成掩模层（7）的步骤; 形成设置在掩模层（7）的侧面并覆盖多晶硅层（6）的一部分的侧壁（8）的工序; 通过使用掩模层（7）和侧壁（8）中的至少一个作为掩模，将杂质（52）掺杂到多晶硅层（5）中的步骤; 以及通过使用掩模层（7）和侧壁（8）中的至少一个作为掩模来蚀刻多晶硅层（5,6）的步骤。

    SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME
    4.
    发明公开
    SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME 审中-公开
    半导体器件及其制造方法

    公开(公告)号：EP1935028A2

    公开(公告)日：2008-06-25

    申请号：EP06796840.4

    申请日：2006-08-22

    申请人： Nissan Motor Company Limited

    发明人： HAYASHI, Tetsuya ,  SHIMOIDA, Yoshio ,  HOSHI, Masakatsu ,  TANAKA, Hideaki ,  YAMAGAMI, Shigeharu

    IPC分类号： H01L29/861 ,  H01L29/24

    CPC分类号： H01L29/861 ,  H01L21/046 ,  H01L29/0623 ,  H01L29/0653 ,  H01L29/1608 ,  H01L29/267 ,  H01L29/6606 ,  H01L29/66068 ,  H01L29/7828

    摘要： A semiconductor device includes: a semiconductor base; a hetero semiconductor region which is in contact with the semiconductor base and which has a band gap different from that of the semiconductor base; a first electrode connected to the hetero semiconductor region; and a second electrode forming an ohmic contact to the semiconductor base. The hetero semiconductor region includes a laminated hetero semiconductor region formed by laminating a plurality of semiconductor layers in which crystal alignment is discontinuous at a boundary between at least two layers.

    摘要翻译： 一种半导体器件包括：半导体基体; 与所述半导体基体接触且具有与所述半导体基体不同的带隙的异质半导体区域; 连接到异质半导体区的第一电极; 以及与半导体基底形成欧姆接触的第二电极。 异质半导体区包括通过层叠在至少两层之间的边界处晶体取向不连续而形成的多个半导体层而形成的层叠异质半导体区。

    SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME
    5.
    发明公开
    SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME 有权
    半导体器件及其制造方法

    公开(公告)号：EP1929534A2

    公开(公告)日：2008-06-11

    申请号：EP06768429.0

    申请日：2006-08-02

    申请人： Nissan Motor Company Limited

    发明人： SHIMOIDA, Yoshio ,  HAYASHI, Tetsuya ,  HOSHI, Masakatsu ,  TANAKA, Hideaki ,  YAMAGAMI, Shigeharu

    IPC分类号： H01L29/267 ,  H01L29/78 ,  H01L21/04 ,  H01L29/24 ,  H01L29/08 ,  H01L29/06

    CPC分类号： H01L29/0847 ,  H01L21/0445 ,  H01L29/0696 ,  H01L29/1608 ,  H01L29/267 ,  H01L29/66068 ,  H01L29/7828

    摘要： A semiconductor device has a semiconductor base of a first conductivity type; a hetero semiconductor region in contact with the semiconductor base; a gate electrode adjacent to a portion of a junction between the hetero semiconductor region and the semiconductor base across a gate insulating film; a source electrode connected to the hetero semiconductor region; and a drain electrode connected to the semiconductor base. The hetero semiconductor region has a band gap different from that of the semiconductor base. The hetero semiconductor region includes a first hetero semiconductor region and a second hetero semiconductor region. The first hetero semiconductor region is formed before the gate insulating film is formed. The second hetero semiconductor region is formed after the gate insulating film is formed.

    摘要翻译： 一种半导体器件具有第一导电类型的半导体基底; 与半导体基极接触的异质半导体区域; 栅极电极，隔着栅极绝缘膜与所述异质半导体区域和所述半导体基极之间的结的一部分相邻; 连接到异质半导体区的源电极; 和连接到半导体基座的漏电极。 异质半导体区具有与半导体基极不同的带隙。 异质半导体区域包括第一异质半导体区域和第二异质半导体区域。 第一异质半导体区域在形成栅极绝缘膜之前形成。 第二异质半导体区域在形成栅极绝缘膜之后形成。