公开(公告)号：EP4369414A3

公开(公告)日：2024-08-14

申请号：EP23198226.5

申请日：2023-09-19

申请人： NXP USA, Inc.

发明人： Saxena, Tanuj ,  Pigott, John ,  Khemka, Vishnu ,  Radic, Ljubo ,  Qin, Ganming

IPC分类号： H01L29/49 ,  H01L29/78 ,  H01L29/861

CPC分类号： H01L29/7804 ,  H01L29/4925 ,  H01L29/1608 ,  H01L29/861

摘要： A semiconductor device has first and second current terminals and a control terminal that can be biased to form an electrically conductive path from the first current terminal to the second current terminal through a channel region and that is provided with a temperature sensitive current limiting device. The current-limiting device is integrally formed from semiconductor material of the control terminal and is configured to cause a reduction in electrical current flowing through the channel region when the temperature of the device in the channel region exceeds a predetermined threshold temperature.

公开(公告)号：EP4369414A2

公开(公告)日：2024-05-15

申请号：EP23198226.5

申请日：2023-09-19

申请人： NXP USA, Inc.

发明人： Saxena, Tanuj ,  Pigott, John ,  Khemka, Vishnu ,  Radic, Ljubo ,  Qin, Ganming

IPC分类号： H01L29/49 ,  H01L29/78

CPC分类号： H01L29/7804 ,  H01L29/4925 ,  H01L29/1608 ,  H01L29/861

摘要： A semiconductor device has first and second current terminals and a control terminal that can be biased to form an electrically conductive path from the first current terminal to the second current terminal through a channel region and is provided with a temperature sensitive current limiting device. The current-limiting device is integrally formed from semiconductor material of the control terminal and is configured to cause a reduction in electrical current flowing through the channel region when the temperature of the device in the channel region exceeds a predetermined threshold temperature.

公开(公告)号：EP3379581A1

公开(公告)日：2018-09-26

申请号：EP18000268.5

申请日：2018-03-19

申请人： 3-5 Power Electronics GmbH

发明人： Volker, Dudek

IPC分类号： H01L29/861 ,  H01L29/872 ,  H01L29/20 ,  H01L29/32 ,  H01L29/36 ,  H01L21/329

CPC分类号： H01L29/8613 ,  H01L21/187 ,  H01L29/20 ,  H01L29/32 ,  H01L29/36 ,  H01L29/66204 ,  H01L29/861 ,  H01L29/872

摘要： Stapelförmige III-V-Halbleiterdiode (10), aufweisend eine n + -Schicht (12) mit einer Dotierstoffkonzentration von mindestens 10 19 N/cm 3 , eine n-Schicht (14) mit einer Dotierstoffkonzentration von 10 12 -10 16 N/cm 3 , einer Schichtdicke (D2) von 10-300 µm, eine p + -Schicht (18) mit einer Dotierstoffkonzentration von 5•10 18 -5•10 20 cm 3 , mit einer Schichtdicke (D3) größer 2 µm, wobei die Schichten in der genannten Reihenfolge aufeinander folgen, und jeweils eine GaAs-Verbindung umfassen, die n + -Schicht (12) oder die p + -Schicht (18) als Substrat ausgebildet ist und eine Unterseite der n-Schicht (14) stoffschlüssig mit einer Oberseite der n + -Schicht (12) verbunden ist, und zwischen der n--Schicht (14) und der p + -Schicht (18) eine dotierte Zwischenschicht (15) angeordnet ist, und mit einer Oberseite und einer Unterseite und die Unterseite der Zwischenschicht (15) mit der Oberseite der n-Schicht (14) sowie die Oberseite der Zwischenschicht mit der Unterseite der p+-Schicht (18) stoffschlüssig verbunden ist, und wobei die Zwischenschicht (16) mit der n-Schicht (14) und mit der p+-Schicht (18) stoffschlüssig verbunden und p-dotiert ist, und die stapelförmige III-V-Halbleiterdiode (10) eine erste Defektschicht (16) mit einer Schichtdicke (D4) größer 0,5 µm umfasst, die Defektschicht (16) innerhalb der p-Schicht angeordnet ist und die Defektschicht (16) eine Defektkonzentration im einem Bereich zwischen 1•10 13 N/cm 3 und 5•10 16 N/cm 3 aufweist.

公开(公告)号：EP3352225A1

公开(公告)日：2018-07-25

申请号：EP15904057.5

申请日：2015-09-15

申请人： Hitachi, Ltd.

发明人： MORI, Yuki ,  SHIMA, Akio

IPC分类号： H01L29/78 ,  H01L29/06 ,  H01L29/861 ,  H01L29/868

CPC分类号： H01L29/7811 ,  B60L15/00 ,  B60L2200/26 ,  H01L21/0465 ,  H01L29/06 ,  H01L29/0623 ,  H01L29/063 ,  H01L29/1095 ,  H01L29/1608 ,  H01L29/167 ,  H01L29/66068 ,  H01L29/78 ,  H01L29/7805 ,  H01L29/861 ,  H01L29/868 ,  H02P27/06

摘要： An object of the present invention is to suppress energization deterioration due to crystal defects in a semiconductor device including SiC-MOSFET. To solve this problem, a semiconductor device of the present invention includes: an n - -type epitaxial layer formed on a main surface of an n + -type SiC substrate; a p-type termination region that is annularly formed in the n - -type epitaxial layer outside an active region; and an n-type hole annihilation region annularly formed in the n - -type epitaxial layer outside the p-type termination region, apart from the p-type termination region. Then, the n-type hole annihilation region has a first end surface facing the p-type termination region, as well as a second end surface on the opposite side of the first end surface. When a depth of the n-type hole annihilation region is d TM , a depth of the p-type termination region is d NR , a thickness of the n - -type epitaxial layer is d Epi , a distance from the first end surface of the n-type hole annihilation region to the second end surface thereof is L NR , and a distance from the first end surface of the n-type hole annihilation region to the periphery of the semiconductor substrate is |X NR |, these variables have the following relationship: d NR ≥d TM , (|X NR |+d NR )≥d Epi , 0 NR NR |

公开(公告)号：EP3320563A1

公开(公告)日：2018-05-16

申请号：EP16711477.6

申请日：2016-03-10

申请人： United Silicon Carbide Inc.

发明人： BHALLA, Anup ,  FURSIN, Leonid

IPC分类号： H01L29/78 ,  H01L29/12

CPC分类号： H01L29/1608 ,  H01L27/0629 ,  H01L29/1095 ,  H01L29/1602 ,  H01L29/2003 ,  H01L29/407 ,  H01L29/42312 ,  H01L29/42364 ,  H01L29/4916 ,  H01L29/51 ,  H01L29/7803 ,  H01L29/7813 ,  H01L29/7828 ,  H01L29/861

摘要： A monolithically integrated MOS channel in gate-source shorted mode is used as a diode for the third quadrant conduction path for a power MOSFET. The MOS diode and MOSFET can be constructed in a variety of configurations including split-cell and trench. The devices may be formed of silicon carbide, gallium nitride, aluminum nitride, aluminum gallium nitride, diamond, or similar semiconductor. Low storage capacitance and low knee voltage for the MOS diode can be achieved by a variety of means. The MOS diode may be implemented with channel mobility enhancement materials, and/or have a very thin/high permittivity gate dielectric. The MOSFET gate conductor and MOS diode gate conductor may be made of polysilicon doped with opposite dopant types. The surface of the MOS diode dielectric may be implanted with cesium.

公开(公告)号：EP2786418B1

公开(公告)日：2018-04-04

申请号：EP12794663.0

申请日：2012-11-12

申请人： Robert Bosch GmbH

发明人： QU, Ning ,  GOERLACH, Alfred

IPC分类号： H01L29/861 ,  H01L29/872

CPC分类号： H01L29/8725 ,  H01L29/0634 ,  H01L29/47 ,  H01L29/861 ,  H01L29/872

公开(公告)号：EP3297029A1

公开(公告)日：2018-03-21

申请号：EP17188615.3

申请日：2017-08-30

申请人： Renesas Electronics Corporation

发明人： NAKAHARA, Yasushi ,  TODA, Tetsu ,  KUROIWA, Hiroshi ,  KANDA, Ryo

IPC分类号： H01L29/40 ,  H01L29/78 ,  H01L29/861 ,  H03K17/0416 ,  H03K17/082

CPC分类号： H02H7/0838 ,  H01L29/405 ,  H01L29/7816 ,  H01L29/861 ,  H02H1/04 ,  H03K17/0416 ,  H03K17/0822

摘要： To realize a reduction in the number of parts in a system including a driver IC (semiconductor device). A high potential side power supply voltage (VP) is applied to a power supply application area (AR_VP). A high side area (AR_HVBK) is formed with a circuit which includes a driver driving a high side transistor (HA) and is operated at a boot power supply voltage (VB) with a floating voltage (VS) as a reference. A low side area (AR_LVBK) is formed with a circuit operated at a power supply voltage (VCC) with a low potential side power supply voltage (COM) as a reference. A first termination area (AR_TRMBK1) is disposed in a ring form so as to surround the power supply application area. A second termination area (AR_TRMBK2) is disposed in a ring form so as to surround the high side area.

摘要翻译： 为了实现包括驱动器IC（半导体器件）的系统中的部件数量的减少。 高电位侧电源电压（VP）被施加到电源施加区域（AR_VP）。 高侧区域（AR_HVBK）由包括驱动高侧晶体管（HA）的驱动器并以浮动电压（VS）作为参考以开机电源电压（VB）运行的电路形成。 低电位侧区域（AR_LVBK）由以低电位侧电源电压（COM）作为基准的电源电压（VCC）工作的电路形成。 第一终端区域（AR_TRMBK1）以围绕供电应用区域的方式配置成环状。 第二终端区域（AR_TRMBK2）以包围高侧区域的方式配置成环状。

公开(公告)号：EP3291305A1

公开(公告)日：2018-03-07

申请号：EP17187811.9

申请日：2017-08-24

申请人： Power Integrations, Inc.

发明人： Ankoudinov, Alexei ,  Georgescu, Sorin ,  Parthasarathy, Vijay ,  Marcum, Kelly E. ,  Bu, Jiankang

IPC分类号： H01L29/423 ,  H01L29/78 ,  H01L29/06

CPC分类号： H01L29/0692 ,  H01L27/0814 ,  H01L27/088 ,  H01L29/0649 ,  H01L29/0696 ,  H01L29/0865 ,  H01L29/0882 ,  H01L29/1095 ,  H01L29/404 ,  H01L29/407 ,  H01L29/4238 ,  H01L29/7395 ,  H01L29/7397 ,  H01L29/7811 ,  H01L29/7813 ,  H01L29/7827 ,  H01L29/861 ,  H01L29/8613

摘要： A semiconductor device including a dummy pillar and a plurality of racetrack pillars. The dummy pillar of semiconductor material extends in a first lateral direction. The plurality of racetrack pillars, including the semiconducting material, surrounds the dummy pillar. Each of the plurality of racetrack pillars has a first linear section, which extends in the first lateral direction, and a first rounded section to form a racetrack shape. The plurality of racetrack pillars includes a first racetrack pillar and a second racetrack pillar. The first racetrack pillar is disposed proximate to the dummy pillar and the second racetrack pillar surrounds the first racetrack pillar. The first racetrack pillar is disposed between the dummy pillar and the second racetrack pillar. The semiconductor device includes a plurality of spacing regions including a first spacing region that surrounds the dummy pillar and is disposed between the first racetrack pillar and the dummy pillar.

摘要翻译： 一种半导体器件，包括伪柱和多个跑道柱。 半导体材料的虚拟柱沿第一横向方向延伸。 包括半导体材料的多个跑道支柱围绕虚拟柱。 多个跑道支柱中的每一个都具有沿第一横向方向延伸的第一线性部分和形成跑道形状的第一圆形部分。 多个跑道支柱包括第一跑道支柱和第二跑道支柱。 第一跑道支柱靠近虚拟立柱设置，而第二跑道支柱围绕第一跑道支柱。 第一跑道支柱布置在虚拟支柱和第二跑道支柱之间。 所述半导体器件包括多个间隔区域，所述多个间隔区域包括围绕所述虚拟柱体并且设置在所述第一跑道柱体和所述虚拟柱体之间的第一间隔区域。

公开(公告)号：EP1690295A4

公开(公告)日：2018-01-24

申请号：EP04813005

申请日：2004-12-06

申请人： INT RECTIFIER CORP

发明人： BEACH ROBERT

IPC分类号： H01L29/739 ,  H01L20060101 ,  H01L31/0328

CPC分类号： H01L29/7786 ,  H01L21/28581 ,  H01L21/28587 ,  H01L23/3171 ,  H01L29/2003 ,  H01L29/402 ,  H01L29/452 ,  H01L29/66143 ,  H01L29/66462 ,  H01L29/861 ,  H01L29/872 ,  H01L29/88 ,  H01L2924/0002 ,  H01L2924/3011 ,  H01L2924/00

摘要： An embodiment of a III-nitride semiconductor device and method for making the same may include a low resistive passivation layer that permits the formation of device contacts without damage to the III-nitride material during high temperature processing. The passivation layer may be used to passivate the entire device. The passivation layer may also be provided in between contacts and active layers of the device to provide a low resistive path for current conduction. The passivation process may be used with any type of device, including FETs, rectifiers, schottky diodes and so forth, to improve breakdown voltage and prevent field crowding effects near contact junctions. The passivation layer may be activated with a low temperature anneal that does not impact the III-nitride device regarding outdiffusion.

公开(公告)号：EP2565922A4

公开(公告)日：2017-11-29

申请号：EP11775053

申请日：2011-04-27

申请人： NISSAN MOTOR

发明人： YAMAGAMI SHIGEHARU ,  HAYASHI TETSUYA ,  SUZUKI TATSUHIRO

IPC分类号： H01L29/78 ,  H01L29/12 ,  H01L29/47 ,  H01L29/872

CPC分类号： H01L21/8213 ,  H01L21/046 ,  H01L21/0485 ,  H01L21/823487 ,  H01L27/0727 ,  H01L29/0619 ,  H01L29/0696 ,  H01L29/1095 ,  H01L29/1602 ,  H01L29/1608 ,  H01L29/165 ,  H01L29/2003 ,  H01L29/6606 ,  H01L29/66068 ,  H01L29/7806 ,  H01L29/7813 ,  H01L29/861 ,  H01L29/872

摘要： An object of the invention is to reduce distance between each pair of adjacent insulating gate portions and thereby miniaturize a semiconductor device. A drift region is provided on a semiconductor substrate; first well regions are provided in upper part of the drift region; and source regions are provided in upper part of the first well regions. Each insulating gate portion forms a channel (a inversion layer) in part of the first well region located between the drift region and source region. A first main electrode forms junctions with part of the drift region exposed in the major surface to constitute unipolar diodes and is connected to the first well regions and the source regions. The plurality of insulating gate portions have linear patterns parallel to each other when viewed in the normal direction of the major surface. Between each pair of adjacent insulating gate portions, junction portions in which the first main electrode forms junctions with the drift region and the first well regions are arranged along the direction that the insulating gate portions extend. The channels are formed at least in the normal direction of the major surface.