利索-全球专利检索

  1. Login
  2. Sign Up

Search Results

15 records (took 0.008 seconds)

    AN ALLOCATION AND ISSUE STAGE FOR REORDERING A MICROINSTRUCTION SEQUENCE INTO AN OPTIMIZED MICROINSTRUCTION SEQUENCE TO IMPLEMENT AN INSTRUCTION SET AGNOSTIC RUNTIME ARCHITECTURE
    2.
    发明公开
    AN ALLOCATION AND ISSUE STAGE FOR REORDERING A MICROINSTRUCTION SEQUENCE INTO AN OPTIMIZED MICROINSTRUCTION SEQUENCE TO IMPLEMENT AN INSTRUCTION SET AGNOSTIC RUNTIME ARCHITECTURE 审中-公开
    配股和输出级微重排命令序列中的强化微命令序列用于实现无关的指令集时体系结构

    公开(公告)号：EP3172666A1

    公开(公告)日：2017-05-31

    申请号：EP15825285.8

    申请日：2015-07-24

    Applicant: INTEL Corporation

    Inventor： ABDALLAH, Mohammad

    IPC: G06F9/455 ,  G06F9/45 ,  G06F9/30 ,  G06F9/38

    CPC classification number: G06F9/45533 ,  G06F9/30174 ,  G06F9/3818 ,  G06F9/3836 ,  G06F9/3867 ,  G06F9/4552

    Abstract: A system for an agnostic runtime architecture. The system includes a system emulation/virtualization converter, an application code converter, and a system converter wherein the system emulation/virtualization converter and the application code converter implement a system emulation process, and wherein the system converter implements a system conversion process for executing code from a guest image. The system converter further comprises an instruction fetch component for fetching an incoming microinstruction sequence, a decoding component coupled to the instruction fetch component to receive the fetched macro instruction sequence and decode into a microinstruction sequence, and an allocation and issue stage coupled to the decoding component to receive the microinstruction sequence perform optimization processing by reordering the microinstruction sequence into an optimized microinstruction sequence comprising a plurality of dependent code groups. A microprocessor pipeline is coupled to the allocation and issue stage to receive and execute the optimized microinstruction sequence. A sequence cache is coupled to the allocation and issue stage to receive and store a copy of the optimized microinstruction sequence for subsequent use upon a subsequent hit on the optimized microinstruction sequence, and a hardware component is coupled for moving instructions in the incoming microinstruction sequence.

    Abstract translation: 一种用于在运行无关的架构体系。 该系统包括一个系统仿真/虚拟化转换器，应用程序代码转换器，和一个系统转换器worin系统仿真/虚拟化转换器和所述应用程序的代码转换器执行一个系统仿真过程，和worin系统变换器实现了系统转换处理，用于执行代码 从客户的形象。 该系统转换器指令进一步包括提取部件，用于传入的微指令序列的读取，耦合到所述指令解码组件抓取组件接收所获取的宏指令序列，并解码成一个微指令序列，并耦合到所述解码组件分配和问题阶段 以接收微指令序列通过重新排序的微指令序列成优化的微指令序列，其包括相关的代码组的多元性执行优化处理。 微处理器流水线耦合到所述分配及发行阶段以接收和执行优化的微指令序列。 序列高速缓存被耦合到分配及发行阶段在随后的命中所述优化的微指令序列以接收和存储用于后续使用的优化的微指令序列的拷贝，和一个硬件组件被耦合以在输入的微指令序列移动的指令。

    TECHNOLOGIES FOR EFFICIENT LZ77-BASED DATA DECOMPRESSION
    5.
    发明公开
    TECHNOLOGIES FOR EFFICIENT LZ77-BASED DATA DECOMPRESSION 审中-公开

    公开(公告)号：EP3198729A4

    公开(公告)日：2018-06-13

    申请号：EP15843355

    申请日：2015-08-24

    Applicant: INTEL CORP

    Inventor： GOPAL VINODH ,  GULLEY SEAN M ,  GUILFORD JAMES D

    IPC: H03M7/30

    CPC classification number: H03M7/3086 ,  G06F3/0604 ,  G06F3/064 ,  G06F3/065 ,  G06F3/0673 ,  G06F9/3818 ,  G06F9/3863 ,  G06F12/023 ,  G06F12/0875 ,  G06F2212/1044 ,  G06F2212/452 ,  H03M7/3091 ,  H03M7/6005 ,  H03M7/6017

    Abstract: Technologies for data decompression include a computing device that reads a symbol tag byte from an input stream. The computing device determines whether the symbol can be decoded using a fast-path routine, and if not, executes a slow-path routine to decompress the symbol. The slow-path routine may include data-dependent branch instructions that may be unpredictable using branch prediction hardware. For the fast-path routine, the computing device determines a next symbol increment value, a literal increment value, a data length, and an offset based on the tag byte, without executing an unpredictable branch instruction. The computing device sets a source pointer to either literal data or reference data as a function of the tag byte, without executing an unpredictable branch instruction. The computing device may set the source pointer using a conditional move instruction. The computing device copies the data and processes remaining symbols. Other embodiments are described and claimed.

    PROCESSORS HAVING FULLY-CONNECTED INTERCONNECTS SHARED BY VECTOR CONFLICT INSTRUCTIONS AND PERMUTE INSTRUCTIONS
    6.
    发明公开
    PROCESSORS HAVING FULLY-CONNECTED INTERCONNECTS SHARED BY VECTOR CONFLICT INSTRUCTIONS AND PERMUTE INSTRUCTIONS 审中-公开
    冲突向量指令和共享PERMUTIERUNGSANWEISUNGEN完全连接环节PROCESSORS

    公开(公告)号：EP2798504A1

    公开(公告)日：2014-11-05

    申请号：EP11878342.2

    申请日：2011-12-29

    Applicant: Intel Corporation

    Inventor： FORSYTH, Andrew Thomas ,  BRADFORD, Dennis R.

    IPC: G06F13/14 ,  G06F9/30 ,  G06F9/305

    CPC classification number: G06F9/30036 ,  G06F9/30021 ,  G06F9/30032 ,  G06F9/30145 ,  G06F9/3818 ,  G06F9/3838

    Abstract: An apparatus includes a decode unit to decode a permute instruction and a vector conflict instruction. A vector execution unit is coupled with the decode unit and includes a fully-connected interconnect. The fully-connected interconnect has at least four inputs to receive at least four corresponding data elements of at least one source vector. The fully-connected interconnect has at least four outputs. Each of the at least four inputs is coupled with each of the at least four outputs. The execution unit also includes a permute instruction execution logic coupled with the at least four outputs and operable to store a first vector result in response to the permute instruction. The execution unit also includes a vector conflict instruction execution logic coupled with the at least four outputs and operable to store a second vector result in a destination storage location in response to the vector conflict instruction.

    TECHNOLOGIES FOR EFFICIENT LZ77-BASED DATA DECOMPRESSION
    10.
    发明公开
    TECHNOLOGIES FOR EFFICIENT LZ77-BASED DATA DECOMPRESSION 审中-公开
    有效的基于LZ77的数据压缩技术

    公开(公告)号：EP3198729A1

    公开(公告)日：2017-08-02

    申请号：EP15843355.7

    申请日：2015-08-24

    Applicant: Intel Corporation

    Inventor： GOPAL, Vinodh ,  GULLEY, Sean M. ,  GUILFORD, James D.

    IPC: H03M7/30

    CPC classification number: H03M7/3086 ,  G06F3/0604 ,  G06F3/064 ,  G06F3/065 ,  G06F3/0673 ,  G06F9/3818 ,  G06F9/3863 ,  G06F12/023 ,  G06F12/0875 ,  G06F2212/1044 ,  G06F2212/452 ,  H03M7/3091 ,  H03M7/6005 ,  H03M7/6017

    Abstract: Technologies for data decompression include a computing device that reads a symbol tag byte from an input stream. The computing device determines whether the symbol can be decoded using a fast-path routine, and if not, executes a slow-path routine to decompress the symbol. The slow-path routine may include data-dependent branch instructions that may be unpredictable using branch prediction hardware. For the fast-path routine, the computing device determines a next symbol increment value, a literal increment value, a data length, and an offset based on the tag byte, without executing an unpredictable branch instruction. The computing device sets a source pointer to either literal data or reference data as a function of the tag byte, without executing an unpredictable branch instruction. The computing device may set the source pointer using a conditional move instruction. The computing device copies the data and processes remaining symbols. Other embodiments are described and claimed.

    Abstract translation: 用于数据解压缩的技术包括从输入流中读取符号标签字节的计算设备。 计算设备确定符号是否可以使用快速路径例程来解码，并且如果否，则执行慢路径例程以解压缩符号。 慢路径例程可以包括可能使用分支预测硬件不可预知的数据相关分支指令。 对于快速路径例程，计算设备基于标签字节确定下一个符号增量值，文字增量值，数据长度和偏移量，而不执行不可预测的分支指令。 计算设备根据标签字节将源指针设置为文字数据或参考数据，而不执行不可预知的分支指令。 计算设备可以使用条件移动指令来设置源指针。 计算设备复制数据并处理剩余的符号。 描述并要求保护其他实施例。

Patent Agency Ranking