COLLAPSIBLE FRONT-END TRANSLATION FOR INSTRUCTION FETCH
    1.
    发明授权
    COLLAPSIBLE FRONT-END TRANSLATION FOR INSTRUCTION FETCH 有权
    指令获取的可折叠前端转换

    公开(公告)号:EP1994471B1

    公开(公告)日:2017-12-13

    申请号:EP07762866.7

    申请日:2007-02-01

    摘要: Address translation for instruction fetching can be obviated for sequences of instruction instances that reside on a same page. Obviating address translation reduces power consumption and increases pipeline efficiency since accessing of an address translation buffer can be avoided. Certain events, such as branch mis-predictions and exceptions, can be designated as page boundary crossing events. In addition, carry over at a particular bit position when computing a branch target or a next instruction instance fetch target can also be designated as a page boundary crossing event. An address translation buffer is accessed to translate an address representation of a first instruction instance. However, until a page boundary crossing event occurs, the address representations of subsequent instruction instances are not translated. Instead, the translated portion of the address representation for the first instruction instance is recycled for the subsequent instruction instances.