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    DATA PROCESSOR
    2.
    发明公开
    DATA PROCESSOR 审中-公开
    数据处理器

    公开(公告)号：EP1962170A4

    公开(公告)日：2010-05-05

    申请号：EP06833915

    申请日：2006-12-04

    申请人： PANASONIC CORP

    发明人： NISHIDA YOICHI ,  EJIMA TAKAYUKI ,  MIYAZAKI AKIHIRO ,  SATO YASUNORI

    IPC分类号： G11B19/02 ,  G06F1/32 ,  G11B19/00 ,  G11B20/10 ,  H04N5/76 ,  H04N5/93

    CPC分类号： G11B20/10 ,  G06F1/3203 ,  G06F1/324 ,  G11B19/02 ,  H04N5/781 ,  H04N5/85 ,  H04N5/907 ,  H04N9/8042 ,  H04N9/8047 ,  H04N9/877 ,  H04N19/44 ,  Y02D10/126 ,  Y02D50/20

    摘要： The present invention provides a data processor which can reduce the power consumption with the continuous compressed data, such as AV reproduction data, broadcast data or the like, to be reproduced, viewed and listened. The data processor comprises a decoder 11 for decoding the compressed data into decoded data while reading the compressed data from a first data storage 21, a second data storage 22 for storing therein the decoded data, a DA converter 41 for converting the decoded data into an analog signal while reading the decoded data from the second data storage 22 in real-time, a first controller 52 for controlling the decoder 11 to perform intermittent operation by executing a process between reading the compressed data and storing the decoded data at a speed faster than real-time, a clock/power controller 54 for making a restriction of power consumption of upstream from the second data storage 22 in downtime of the intermittent operation, a second controller 53 for outputting a control signal in accordance with the storage state of the decoded data stored in the second data storage 22, and an activation controller 55 for controlling the clock/power controller 54 to lift the restriction of the power consumption in response to reception of the control signal.