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    Circuit arrangement for processing sampled analogue electrical signals
    3.
    发明公开
    Circuit arrangement for processing sampled analogue electrical signals 失效
    用于处理采样模拟电路信号的电路布置

    公开(公告)号：EP0322063A3

    公开(公告)日：1991-09-11

    申请号：EP88202948.1

    申请日：1988-12-19

    申请人： PHILIPS ELECTRONICS UK LIMITED ,  Philips Electronics N.V.

    发明人： Hughes, John Barry

    IPC分类号： G11C27/02

    CPC分类号： G11C27/028 ,  G11C27/02

    摘要： A circuit arrangement for processing sampled analogue electrical signals, each sample being in the form of a current, comprises means for combining, in predetermined proportions, the input sample current in the present sample period with current(s) derived from input sample current(s) in one or more preceding sample periods and means for deriving the processed output signal from the combined current produced by the combining means in successive sample periods. The circuit arrangement is formed by a plurality of circuit modules, for example scaling, memory, and integrator modules, each of which may be capable only of processing uni-directional currents. To enable easy interconnection of the modules, each module is arranged to receive and deliver bi-directional currents and to generate internally bias currents to enable conversion from bi-directional to uni-directional currents and vice versa.

    Integrator circuit
    4.
    发明公开
    Integrator circuit 失效
    积分电路

    公开(公告)号：EP0372649A3

    公开(公告)日：1991-07-10

    申请号：EP89203069.3

    申请日：1989-12-04

    申请人： PHILIPS ELECTRONICS UK LIMITED ,  Philips Electronics N.V.

    发明人： Hughes, John Barry

    IPC分类号： G11C27/02 ,  G06G7/184

    CPC分类号： G06G7/184 ,  G11C27/028

    摘要： A bilinear integrator comprises a first input (1) and a second input (5). The input (1) is connected to the input of a first current memory cell formed by two transistors (T1, T2), capacitor (C1), and switch (S1). The first current memory cell is arranged to store a current applied to its input during a first portion φ of each sampling period and to reproduce that current at its output during a second portion φ of the succeeding sampling period. The second input (5) is connected to the input of a second current memory cell formed by three transistors (T3, T4 and T5), capacitor (C2) and switch (S3) via the switch (S2). During a second portion φ of each sampling period the current applied to the second input (5) and the current produced at the output of the first current memory cell are applied to the input of the second current memory cell. The second current memory cell has two outputs (from the drain electrodes of transistors (T4, T5)). The first output is fed back to the input of the first current memory cell while the second output is fed to the integrator output (8).

    摘要翻译： 双线性积分器包括第一输入（1）和第二输入（5）。 输入端（1）连接到由两个晶体管（T1，T2），电容器（C1）和开关（S1）形成的第一电流存储单元的输入端。 第一电流存储器单元被布置为存储在每个采样周期的第一部分期间施加到其输入端的电流并且在后续采样周期的第二部分期间在其输出端处再现该电流。 第二输入端（5）通过开关（S2）连接到由三个晶体管（T3，T4和T5），电容器（C2）和开关（S3）形成的第二电流存储单元的输入端。 在每个采样周期的第二部分期间，施加到第二输入端（5）的电流和在第一电流存储单元的输出端产生的电流被施加到第二电流存储单元的输入端。 第二电流存储单元具有两个输出（来自晶体管（T4，T5）的漏电极））。 第一个输出反馈到第一个当前存储单元的输入，而第二个输出送到积分器输出（8）。

    Differentiator circuit
    5.
    发明公开
    Differentiator circuit 失效
    Differenzierschaltung。

    公开(公告)号：EP0416699A1

    公开(公告)日：1991-03-13

    申请号：EP90202343.1

    申请日：1990-09-04

    申请人： PHILIPS ELECTRONICS UK LIMITED ,  Philips Electronics N.V.

    发明人： Hughes, John Barry

    IPC分类号： G06G7/18

    CPC分类号： G06G7/184

    摘要： The differentiator circuit comprises a first current memory cell comprising capacitor C2, switch S2, transistor T2 and transistor T3 and a second current memory cell comprising capacitor C1, switch S1 and transistor T1. During one portion φ2 of each sampling period the input current i minus the current produced by transistor T1, which acts as a current source when switch S1 is open, together with appropriate bias currents to allow bi-directional input currents to be handled is fed via switch S3 to the first current memory cell. During another portion φ1 of each sampling period the input current plus an appropriate bias current is fed to the input of the second current memory cell. The switches S3 and S2 are open so transistor T2 acts as a current source giving an output via switch 54 at output 17 in addition to the output 15. The differentiated output signal is available throughout at output 15 but only during the portion φ2 of each sampling period at output 17.
    The circuit corresponds to a backward Euler mapping from continuous time ideal differentiators. Corresponding circuits giving forward Euler and bilinear mappings are also disclosed as are circuits for lossy differentiators. Various alternative current memory cells are also disclosed.

    摘要翻译： 微分电路包括包括电容器C2，开关S2，晶体管T2和晶体管T3的第一电流存储单元，以及包括电容器C1，开关S1和晶体管T1的第二电流存储单元。 在每个采样周期的一部分phi 2期间，输入电流i减去由开关S1断开时用作电流源的晶体管T1产生的电流以及适当的偏置电流以允许双向输入电流被处理 经由开关S3到第一当前存储单元。 在每个采样周期的另一部分phi 1期间，将输入电流加上适当的偏置电流馈送到第二当前存储单元的输入端。 开关S3和S2断开，以便晶体管T2作为电流源，除了输出端15之外，还通过开关54在输出端17提供输出。微分输出信号在输出15处可用，但仅在每个输出端的部分phi 2期间 输出端17的采样周期。电路对应于来自连续时间理想微分器的后向欧拉映射。 给出给出欧拉和双线性映射的相应电路也被公开为有损差分器的电路。 还公开了各种备选的当前存储器单元。

    Temperature sensing circuit
    6.
    发明公开
    Temperature sensing circuit 失效
    Schaltung zur Messung der Temperatur。

    公开(公告)号：EP0369530A2

    公开(公告)日：1990-05-23

    申请号：EP89202837.4

    申请日：1989-11-08

    申请人： PHILIPS ELECTRONICS UK LIMITED ,  Philips Electronics N.V.

    发明人： Armstrong, Desmond Ross ,  Hughes, John Barry

    IPC分类号： G01K7/00

    CPC分类号： G01K7/01 ,  G01K3/005 ,  Y10S323/907

    摘要： In order to sense the temperature of an integrated circuit chip, a semiconductor junction device (D1) integrated on the chip is used to generate a first signal (V₁) having a known variation with temperature. A second signal (V₂) is generated by passing a PTAT current (I₂) through a resistor (R1) so that the second signal (V₂) has a known variation with temperature which is opposite in sign to that of the first signal (V₁). The two signals are compared (42) to generate an output signal (0T) which is dependent on whether the temperature of the chip is below or above a predetermined threshold temperature. The current (I₁) through the junction device (D1) is also PTAT, enabling a more accurate definition of the threshold temperature in terms of integrated circuit parameters.

    摘要翻译： 为了感测集成电路芯片的温度，集成在芯片上的半导体结器件（D1）用于产生具有已知温度变化的第一信号（V1）。 通过使PTAT电流（I2）通过电阻器（R1）使得第二信号（V2）具有与第一信号（V1）的温度相反的温度的已知变化而产生第二信号（V2） 。 两个信号被比较（42）以产生取决于芯片的温度是否低于或高于预定阈值温度的输出信号（0T）。 通过接合装置（D1）的电流（I1）也是PTAT，使得能够根据集成电路参数更准确地定义阈值温度。

    Circuit arrangement for processing sampled analogue electrical signals
    7.
    发明公开
    Circuit arrangement for processing sampled analogue electrical signals 失效
    Schaltungsanordnung zur Verarbeitung abgetasteter elektrischer analoger Signale。

    公开(公告)号：EP0322063A2

    公开(公告)日：1989-06-28

    申请号：EP88202948.1

    申请日：1988-12-19

    申请人： PHILIPS ELECTRONICS UK LIMITED ,  Philips Electronics N.V.

    发明人： Hughes, John Barry

    IPC分类号： G11C27/02

    CPC分类号： G11C27/028 ,  G11C27/02

    摘要： A circuit arrangement for processing sampled analogue electrical signals, each sample being in the form of a current, comprises means for combining, in predetermined proportions, the input sample current in the present sample period with current(s) derived from input sample current(s) in one or more preceding sample periods and means for deriving the processed output signal from the combined current produced by the combining means in successive sample periods.
    The circuit arrangement is formed by a plurality of circuit modules, for example scaling, memory, and integrator modules, each of which may be capable only of processing uni-directional currents. To enable easy interconnection of the modules, each module is arranged to receive and deliver bi-directional currents and to generate internally bias currents to enable conversion from bi-directional to uni-directional currents and vice versa.

    摘要翻译： 一种用于处理采样的模拟电信号的电路装置，每个样本是电流形式，包括用于以预定比例将当前采样周期中的输入采样电流与从输入采样电流（s）导出的电流 ），以及用于在连续采样周期中从由组合装置产生的组合电流导出经处理的输出信号的装置。 电路装置由多个电路模块形成，例如缩放，存储器和积分器模块，每个电路模块只能处理单向电流。 为了实现模块的简单互连，每个模块被布置为接收和传送双向电流并产生内部偏置电流，以实现从双向电流到单向电流的转换，反之亦然。

    Electrical filter
    8.
    发明公开
    Electrical filter 失效
    电过滤器

    公开(公告)号：EP0244020A2

    公开(公告)日：1987-11-04

    申请号：EP87200758.8

    申请日：1987-04-23

    申请人： PHILIPS ELECTRONICS UK LIMITED ,  Philips Electronics N.V.

    发明人： Hughes, John Barry

    IPC分类号： H03H11/12 ,  H03J3/24

    CPC分类号： H03H11/12 ,  H03J3/24

    摘要： An integrated electrical filter includes resistors (R10-12) and capacitors (C10-12). The capacitors are controllable in value by means of a control circuit (100-109) and are formed by a binary weighted array of capacitor elements which are selectively connectable in parallel. A controlled oscillator (103 Figure 1) or a controlled phase shifting network (113 Figure 2) includes a capacitor of the same form as the filter capacitors. The oscillator (103) or phase shifter (113) form part of a phase locked loop (101, 104, 105, 107) which produces a digital code as its control signal at the output of an up/down counter (107). This digital code is latched in a register (109) to provide a control signal for the filter capacitors and is used directly to control the capacitor(s) in the controlled oscillator or phase shifter.

    摘要翻译： 集成电路滤波器包括电阻（R10-12）和电容（C10-12）。 这些电容器借助于控制电路（100-109）是可控制的，并且由可选择地可并联连接的电容器元件的二进制加权阵列形成。 受控振荡器（图1的103）或受控相移网络（图2的113）包括与滤波电容器形式相同的电容器。 振荡器（103）或移相器（113）形成锁相环（101,104,105,107）的一部分，该锁相环在增/减计数器（107）的输出端产生数字码作为其控制信号。 该数字码被锁存在寄存器（109）中以提供用于滤波电容器的控制信号，并直接用于控制受控振荡器或移相器中的电容器。