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公开(公告)号：EP1297521A1
公开(公告)日：2003-04-02
申请号：EP01948433.6
申请日：2001-06-18
发明人： EVOY, David, R.
CPC分类号： G09G3/2018 , G09G3/3622 , G09G2320/0247
摘要： A method for providing intensity modulation for a display of an electronic device. The method uses tables of ratios for generating color modulation patterns. The method includes the step of defining a table of intensity values with each intensity value including a respective on-ratio and a respective off-ratio. A pixel intensity for a pixel of a display is selected by selecting a corresponding intensity value in the table. The pixel intensity is implemented by using an accumulator having an output for determining whether the pixel is on or off, wherein the pixel is on for zero and for positive values of the output and off for negative values of the output. The output is used to implement a duty cycle for the pixel, by turning the pixel on and off. The duty cycle is implemented by setting an initial output of the accumulator. The output is subsequently set to a value equal to the output minus the off-ratio if the pixel is on, and setting the output to the output plus the on-ratio if the pixel is off. Successively turning the pixel on and off in accordance with the output thereby implements a duty cycle for the pixel according to the on-ratio and off-ratio of the intensity value.
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公开(公告)号：EP1397748A2
公开(公告)日：2004-03-17
申请号：EP02735695.5
申请日：2002-05-29
CPC分类号： H04L7/0008 , H04L25/14
摘要： In one example embodiment, a high-speed parallel-data communication approach transfers digital data in parallel from a first module to a second module over a communication channel including a plurality of parallel data-carrying lines and a clock path. The parallel bus lines are arranged in a plurality of groups, each of the groups including a plurality of data-carrying lines and a clock path adapted to carry a clock signal for synchronizing digital data carried from the first module to the second module. The sets of data are concurrently transferred using the groups of lines of the parallel bus, and at the second module and for each group, the transferred digital data is synchronously collected via the clock signal for the group. At the second module, the data collected for each group is aligned. By grouping the bus lines in groups with each group having its own clock domain, skew across clock-domain groups is tolerated and overcome by processing the data and the skew first within each clock domain group, and then between groups.
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公开(公告)号：EP1451698B1
公开(公告)日：2006-11-02
申请号：EP02781542.2
申请日：2002-11-14
IPC分类号： G06F13/42
CPC分类号： G06F13/126
摘要： A communication protocol provides high-speed transfers of parallel data between an origination end and a destination end. The protocol involves regularly transmitting data from the origination end to the destination end, including transmitting idle data from the origination end when the destination end is busy and during periods when no commands, data or statuses are pending. When the destination end is not busy, data is sent from the origination end to the destination end by: sequentially transferring read or write commands and, according to a write protocol, pending write data; and transmitting idle packets during periods when no commands are pending. When the origination end is not busy, data is sent from the destination end to the origination end by: sequentially transferring pending end-of-write statuses; sequentially transferring pending read data and read statuses packets according to a read protocol during periods when no end-of-write statuses are pending; and transmitting idle packets during periods when no read data or read status are pending.
摘要翻译： 通信协议提供始发端和目的端之间的并行数据的高速传输。 该协议包括定期从始发端向目的端传输数据，包括当目的端繁忙时以及在没有命令，数据或状态未决时传输来自始端的空闲数据。 当目的端不繁忙时，通过以下方式将数据从始发端发送到目的端：依次传送读取或写入命令，并且根据写入协议，等待写入数据; 并在没有命令等待期间传输空闲数据包。 当起始端不忙时，通过以下方式将数据从目的地端发送到起始端：依次传送未决的结束写状态; 在没有写入结束状态待决的时段期间，根据读协议顺序传送未决读数据和读状态数据包; 并在没有读取数据或读取状态待定的时段期间传输空闲分组。
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公开(公告)号：EP1451698A2
公开(公告)日：2004-09-01
申请号：EP02781542.2
申请日：2002-11-14
IPC分类号： G06F13/42
CPC分类号： G06F13/126
摘要： A communication protocol provides high-speed transfers of parallel data between an origination end and a destination end. The protocol involves regularly transmitting data from the origination end to the destination end, including transmitting idle data from the origination end when the destination end is busy and during periods when no commands, data or statuses are pending. When the destination end is not busy, data is sent from the origination end to the destination end by: sequentially transferring read or write commands and, according to a write protocol, pending write data; and transmitting idle packets during periods when no commands are pending. When the origination end is not busy, data is sent from the destination end to the origination end by: sequentially transferring pending end-of-write statuses; sequentially transferring pending read data and read statuses packets according to a read protocol during periods when no end-of-write statuses are pending; and transmitting idle packets during periods when no read data or read status are pending.
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公开(公告)号：EP1442550B1
公开(公告)日：2006-12-13
申请号：EP02772679.3
申请日：2002-10-02
CPC分类号： H04L7/02 , G06F5/10 , G06F2205/102 , H04L7/0008 , H04L7/005
摘要： A method and arrangement of passing data from a source clock domain to a non-synchronous receive clock domain are provided. A first processing circuit, located in the source clock domain, links write-address information with the data, and a clock generator generates a transmit clock signal in the source clock domain synchronous with a source clock. The first processing circuit transmits the clock signal and the data with the linked write-address information to a second processing circuit in the receive clock domain. In the receive clock domain, the second processing circuit writes the data at an address designating a storage element corresponding to the linked write-address information. The second processing circuit clocks the data into the storage element synchronous with the accompanying transmit clock signal responsive to a write enable signal from the source clock domain, and reads the data out of the storage element synchronous with a receive domain clock.
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公开(公告)号：EP1407366B1
公开(公告)日：2006-10-04
申请号：EP02733069.5
申请日：2002-05-28
发明人： SVESTKA, Ivan , SESSIONS, D., C. , EVOY, David, R.
IPC分类号： G06F13/00
CPC分类号： G06F13/4086 , Y02D10/14 , Y02D10/151
摘要： In one example embodiment involving a high-speed parallel-data communication from a first module to a second module, a termination circuit is adapted to reduce power consumption at the second module. The termination circuit includes resistive circuits respectively coupled to a plurality of parallel data-carrying lines that form the data bus. The other ends of the resistive circuits are interconnected to provide a reference voltage using the data on the parallel data-carrying lines. Consistent with one embodiment of the present invention, the communication approach uses data sets encoded so that each data set includes the same number of ones and zeroes; in this manner the reference voltage is always at midpoint and useful in providing termination to the data-carrying lines at all times.
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公开(公告)号：EP1407366A2
公开(公告)日：2004-04-14
申请号：EP02733069.5
申请日：2002-05-28
发明人： SVESTKA, Ivan , SESSIONS, D., C. , EVOY, David, R.
IPC分类号： G06F13/00
CPC分类号： G06F13/4086 , Y02D10/14 , Y02D10/151
摘要： In one example embodiment involving a high-speed parallel-data communication from a first module to a second module, a termination circuit is adapted to reduce power consumption at the second module. The termination circuit includes resistive circuits respectively coupled to a plurality of parallel data-carrying lines that form the data bus. The other ends of the resistive circuits are interconnected to provide a reference voltage using the data on the parallel data-carrying lines. Consistent with one embodiment of the present invention, the communication approach uses data sets encoded so that each data set includes the same number of ones and zeroes; in this manner the reference voltage is always at midpoint and useful in providing termination to the data-carrying lines at all times.
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公开(公告)号：EP1728170A2
公开(公告)日：2006-12-06
申请号：EP05718562.1
申请日：2005-03-19
发明人： EVOY, David, R.
IPC分类号： G06F13/42
CPC分类号： G06F13/4295
摘要： A communications arrangement is implemented for tag-field type communications signaling. According to an example embodiment of the present invention, a communications arrangement, such as a PCI Express type arrangement, is configurable for communicating over a communications link using a tag (or similar) available field. According to an example embodiment of the present invention involving PCI Express communications, a first PCI Express endpoint device (150) is adapted to communicate selected information (e.g., synchronous event signals) to a second PCI Express endpoint device (152) using the tag field of data posted to a PCI Express communications link (130). The tag field is set to indicate a characteristic of the synchronous event, and passed from the first PCI Express endpoint device to the second PCI Express endpoint device.
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公开(公告)号：EP1442550A2
公开(公告)日：2004-08-04
申请号：EP02772679.3
申请日：2002-10-02
CPC分类号： H04L7/02 , G06F5/10 , G06F2205/102 , H04L7/0008 , H04L7/005
摘要： A method and arrangement of passing data from a source clock domain to a non-synchronous receive clock domain are provided. A first processing circuit, located in the source clock domain, links write-address information with the data, and a clock generator generates a transmit clock signal in the source clock domain synchronous with a source clock. The first processing circuit transmits the clock signal and the data with the linked write-address information to a second processing circuit in the receive clock domain. In the receive clock domain, the second processing circuit writes the data at an address designating a storage element corresponding to the linked write-address information. The second processing circuit clocks the data into the storage element synchronous with the accompanying transmit clock signal responsive to a write enable signal from the source clock domain, and reads the data out of the storage element synchronous with a receive domain clock.
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10.发明公开ON THE FLY DATA TRANSFER BETWEEN RGB AND YCRCB COLOR SPACES FOR DCT INTERFACE 审中-公开之间的RGB和YCrCb的色彩空间立即使用数据传输DCTSCNITTSTELLE
公开(公告)号：EP1338151A2
公开(公告)日：2003-08-27
申请号：EP01996976.5
申请日：2001-11-13
发明人： EVOY, David, R.
IPC分类号： H04N9/64
CPC分类号： H04N9/64 , H04N19/186 , H04N19/60
摘要： A method for transferring data on the fly between an RGB color space and a YCrCb color space useful for a DCT block-computation engine significantly increases throughput and decreases processor overhead. According to one example embodiment, data is transferred from an RGB color space memory to a YCrCb color space memory in a form useful for presentation to a DCT block-computation engine. In response to accessing the RBG color space memory, the RBG values are asynchronously written to YCrCb intermediate buffers so that one of the YCrCb intermediate buffers is filled through sub-sampling in a manner useful for the DCT block-computation engine while another of the YCrCb intermediate buffers is still being filled. The DCT block-computation engine then accessed the filled YCrCb intermediate buffers while the other of the YCrCb intermediate buffers continues to collect RGB values from the RGB color space memory for the next DCT computation. Other aspects are directed to conversion of the RGB color space to the YCrCb color space using, respectively, a block-by-block conversion, a line-by-line conversion, and a word-by-word conversion.
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