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公开(公告)号：EP1297430A2
公开(公告)日：2003-04-02
申请号：EP01906724.8
申请日：2001-01-26
IPC分类号： G06F13/00
CPC分类号： G06F13/4226
摘要： A data transaction access system for an embedded microprocessor coupled to a PCMCIA bus device. A bus master and a host bus adapter are couple d to a local bus for enabling communication between the bus master and a PCMCIA device. The PCMCIA device is coupled to the host bus adapter via a PCMCIA bus. The bus master uses the local bus to communicate with the PCMCIA device via the host bus adapter. A wait register is coupled to the host bus adapter to receive a delay input from the PCMCIA device describing a latency period of the device when completing a data transaction. Where the latency period described by the delay input is less than a predetermined amount, the host bus adapter is configured to insert wait states into the data transaction of the bus master. When the latency period is greater than the predetermined amount, the host bus adapter is configured to retry the data transaction of the bus master. Alternatively, the wait register is adapted to couple the delay input to the bus master such that the bus master initiates a subsequent access to the PCMCIA device at the expiration of the latency period in order to efficiently complete the subsequent access to the target PCI agent. Alternatively, the wait register is coupled to an arbiter such that the arbiter does not grant the local bus to the bus master for a subsequent access until the expiration of the latency period.
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公开(公告)号：EP1295210A2
公开(公告)日：2003-03-26
申请号：EP01944419.9
申请日：2001-06-11
IPC分类号： G06F13/28
CPC分类号： G06F13/364 , G06F13/28 , Y02D10/14
摘要： A novel and sophisticated direct memory access (DMA) controller that can operate in either "fly-by" mode, "dual-cycle" mode, or "flow-through" mode. The DMA controller of the present embodiment supports a parametrizable number of channels, each of the channels providing support for one of the prior-noted modes of operation. The DMA controller of the present embodiment serves as bus master on the host bus and has the ability to interface with all the devices on the system. The DMA controller of the present embodiment is also optimized for zero wait state sequential transfers on the host bus. Further, the DMA controller of the present embodiment also houses an internal arbiter with programmable priority to choose arbitrate between the different channels, should more than one master that interface to the DMA controller request access to the host bus. An advantage of the present invention is that, because bus master devices are be off-loaded from the host bus, system performance can be dramatically improved. Another advantage is that the present invention provides an easy means for adding more devices to the system.
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公开(公告)号：EP1295210B1
公开(公告)日：2006-06-14
申请号：EP01944419.9
申请日：2001-06-11
IPC分类号： G06F13/28
CPC分类号： G06F13/364 , G06F13/28 , Y02D10/14
摘要： A novel and sophisticated direct memory access (DMA) controller that can operate in either "fly-by" mode, "dual-cycle" mode, or "flow-through" mode. The DMA controller of the present embodiment supports a parametrizable number of channels, each of the channels providing support for one of the prior-noted modes of operation. The DMA controller of the present embodiment serves as bus master on the host bus and has the ability to interface with all the devices on the system. The DMA controller of the present embodiment is also optimized for zero wait state sequential transfers on the host bus. Further, the DMA controller of the present embodiment also houses an internal arbiter with programmable priority to choose arbitrate between the different channels, should more than one master that interface to the DMA controller request access to the host bus. An advantage of the present invention is that, because bus master devices are be off-loaded from the host bus, system performance can be dramatically improved. Another advantage is that the present invention provides an easy means for adding more devices to the system.
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4.发明公开
公开(公告)号：EP1086430A1
公开(公告)日：2001-03-28
申请号：EP00915742.1
申请日：2000-02-04
IPC分类号： G06F13/40
CPC分类号： G06F13/4018 , G06F13/4031
摘要： A method for optimizing the performance of a 64-bit PCI initiator when transferring a 64-bit data via a 64-bit PCI bus. The 64-bit PCI initiator receives a single 64-bit data for transfer via the 64-bit PCI bus. The 64-bit PCI initiator breaks the 64-bit data into a first 32-bit data and a second 32-bit data. The 64-bit initiator then initiates a data transaction with the target device arbitrating for ownership of the 64-bit PCI bus. Upon receiving the ownership of the 64-bit PCI bus, the 64-bit PCI initiator transfers the first 32-bit data and then transfers the second 32-bit data to the target device via the 64-bit PCI bus. The first 32-bit data and the second 32-bit data are transferred by the 64-bit PCI initiator to the target device without the assertion of a REQ64# signal, such that a REQ64# ACK64# protocol is avoided, enabling a more efficient completion of the data transaction.
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公开(公告)号：EP1137998A1
公开(公告)日：2001-10-04
申请号：EP99964165.7
申请日：1999-12-08
IPC分类号： G06F13/42
CPC分类号： G06F13/4004 , G06F13/423
摘要： A system and method for preventing address aliasing when using a single address cycle to transmit a target address in a computer system that includes target devices having addresses of different ranges. The computer system comprises a bus, an initiator device coupled to the bus, a first target device coupled to the bus, and a second target device coupled to the bus. The first target device has a first address range comprising a plurality of bits, and the second target device has a second address range comprising a fewer number of bits than the first address range. The initiator device transmits a signal indicating the size of the target address and also separately transmits in a single address cycle the target address. The second target device disables its address decode logic in response to the signal from the initiator device provided that the size of the target address is greater than the second address range. The second target device is thus prevented from responding to the target address, thereby preventing address aliasing.
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