LOWER POWER HIGH SPEED DECODING BASED DYNAMIC TRACKING FOR MEMORIES

    公开(公告)号:EP3510596A1

    公开(公告)日:2019-07-17

    申请号:EP17755399.7

    申请日:2017-08-11

    摘要: A memory is disclosed. The memory includes a memory array having a plurality of memory cells. The memory also includes an address decoder configured to assert a wordline to enable the memory cells. Additionally, the memory includes a tracking circuit configured to vary a duration of asserting the wordline as a function of which one of the memory cells is accessed. A method is also disclosed. The method includes asserting a wordline to enable the memory cells and varying a duration of asserting the wordline as a function of which one of a plurality of memory cells is accessed.