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    HIGH-SPEED PROGRAMMABLE CLOCK DIVIDER
    1.
    发明公开
    HIGH-SPEED PROGRAMMABLE CLOCK DIVIDER 有权

    公开(公告)号：EP3350928A1

    公开(公告)日：2018-07-25

    申请号：EP16754368.5

    申请日：2016-08-10

    申请人： Qualcomm Incorporated

    发明人： AGRAWAL, Neha ,  MOHAMAD, Sajin ,  LEE, Chulkyu

    IPC分类号： H03K21/10 ,  H03K23/64

    CPC分类号： H03K7/06 ,  G06F1/08 ,  H03K3/037 ,  H03K19/21 ,  H03K21/00 ,  H03K21/026 ,  H03K21/10 ,  H03K23/00 ,  H03K23/64

    摘要： Systems and methods for dividing input clock signals by programmable divide ratios can produce output clock signals with the delay from the input clock signal to the output clock signal independent of the value of the divide ratio and with the duty cycle of the output clock signal being 50% independent of the value of the divide ratio. An example programmable clock divider includes a modulo N counter that produces a count signal that counts modulo the divide ratio and a half-rate clock signal generator that produces a common half-rate clock signal, an even half-rate clock signal, and an odd half-rate clock signal that toggle at one-half the rate of the output clock signal. The common half-rate clock signal, the even half-rate clock signal, and the odd half-rate clock signal are combined to produce the output clock signal.