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    COMMUNICATION AND SYNAPSE TRAINING METHOD AND HARDWARE FOR BIOLOGICALLY INSPIRED NETWORKS
    2.
    发明公开
    COMMUNICATION AND SYNAPSE TRAINING METHOD AND HARDWARE FOR BIOLOGICALLY INSPIRED NETWORKS 审中-公开
    KOMMUNIKATIONS- UND TRAININGSVERFAHREN UND HARDWAREFÜRBIOLOGISCH INSPIRIERTE NETZWERKE

    公开(公告)号：EP2591451A1

    公开(公告)日：2013-05-15

    申请号：EP11733757.6

    申请日：2011-07-07

    申请人： Qualcomm Incorporated

    发明人： APARIN, Vladimir ,  TANG, Yi

    IPC分类号： G06N3/063

    CPC分类号： G06N3/0635 ,  G06N3/02 ,  G06N3/06 ,  G06N3/08 ,  G06N99/005

    摘要： Certain embodiments of the present disclosure support techniques for training of synapses in biologically inspired networks. Only one device based on a memristor can be used as a synaptic connection between a pair of neurons. The training of synaptic weights can be achieved with a low current consumption. A proposed synapse training circuit may be shared by a plurality of incoming/outgoing connections, while only one digitally implemented pulse-width modulation (PWM) generator can be utilized per neuron circuit for generating synapse-training pulses. Only up to three phases of a slow clock can be used for both the neuron-to-neuron communications and synapse training. Some special control signals can be also generated for setting up synapse training events. By means of these signals, the synapse training circuit can be in a high-impedance state outside the training events, thus the synaptic resistance (i.e., the synaptic weight) is not affected outside the training process.

    摘要翻译： 本公开的某些实施例支持在生物启发网络中训练突触的技术。 只有一个基于忆阻器的设备可以用作一对神经元之间的突触连接。 突触体重的训练可以用低电流消耗来实现。 所提出的突触训练电路可以由多个输入/输出连接共享，而每个神经元电路只能使用一个数字实现的脉宽调制（PWM）发生器来产生突触训练脉冲。 只有三个阶段的慢时钟可用于神经元到神经元通信和突触训练。 还可以生成一些特殊控制信号来设置突触训练事件。 通过这些信号，突触训练电路可以处于训练事件之外的高阻抗状态，因此突触电阻（即突触重量）在训练过程之外不受影响。

    DEVICES AND METHODS FOR REDUCING NOISE IN DIGITALLY CONTROLLED OSCILLATORS
    6.
    发明公开
    DEVICES AND METHODS FOR REDUCING NOISE IN DIGITALLY CONTROLLED OSCILLATORS 审中-公开
    器件和方法中的噪声数字控制振荡器还原

    公开(公告)号：EP3020133A1

    公开(公告)日：2016-05-18

    申请号：EP14747193.2

    申请日：2014-07-07

    申请人： Qualcomm Incorporated

    发明人： BALLANTYNE, Gary, John ,  SUN, Bo ,  TANG, Yi ,  YANG, Zixiang ,  ENSAFDARAN, Masoud

    IPC分类号： H03L7/099

    CPC分类号： H03L7/0991 ,  H03B5/1265 ,  H03B2200/0088 ,  H03B2201/025 ,  H03B2202/017 ,  H03J5/24 ,  H03J2200/10 ,  H03J2200/36 ,  H03L7/099 ,  H03L2207/50

    摘要： One feature pertains to a digitally controlled oscillator (DCO) that comprises a variable capacitor and noise reduction circuitry. The variable capacitor has a variable capacitance value that controls an output frequency of the DCO. The variable capacitance value is based on a first bank capacitance value provided by a first capacitor bank, a second bank capacitance value provided by a second capacitor bank, and an auxiliary bank capacitance value provided by an auxiliary capacitor bank. The noise reduction circuitry is adapted to adjust the variable capacitance value by adjusting the auxiliary bank capacitance value while maintaining at least one of the first bank capacitance value and/or the second bank capacitance value substantially unchanged. Prior to adjusting the variable capacitance value, the noise reduction circuitry may determine that a received input DCO control word transitions across a capacitor bank sensitive boundary.

    摘要翻译： 一个特征涉及一种数字控制振荡器（DCO）做包括一可变电容器和噪声降低电路。 可变电容器具有可变电容值做了DCO的输出频率的控制。 可变电容值是基于由第一电容器组，由第二电容器组提供的第二银行电容值，并通过在辅助电容器组提供辅助银行电容值提供第一组电容值。降噪电路是angepasst 通过调整辅助银行电容值，同时保持所述第一银行电容值中的至少一个和/或所述第二隔堤电容值基本不变，以调整可变电容值。 之前调节可变电容值，降噪电路可以确定性矿做跨电容器组敏感边界的接收到的输入DCO控制字转换。

    MIXED SIGNAL TDC WITH EMBEDDED T2V ADC
    7.
    发明公开
    MIXED SIGNAL TDC WITH EMBEDDED T2V ADC 审中-公开
    具有混合信号和嵌入式T2V模拟数字转换器时间数字转换器

    公开(公告)号：EP2972598A2

    公开(公告)日：2016-01-20

    申请号：EP14714891.0

    申请日：2014-03-12

    申请人： Qualcomm Incorporated

    发明人： TANG, Yi ,  SUN, Bo

    IPC分类号： G04F10/00 ,  H03L7/08

    摘要： A time-to-digital converter converts the difference between transition times of a reference clock signal and an oscillating signal to a digital signal whose value is proportional to the transitions timing difference. The time-to-digital converter includes an edge detector, a time-to-voltage converter, and an analog-to-digital converter. The edge detector is adapted to detect, during each period of the reference clock signal, the edge (transition) of the oscillating signal that is closest to the edge of the reference clock signal. The time-to-voltage converter is adapted to generate an analog signal proportional to a difference in time between the detected edge of the oscillating signal and the edge of the reference clock signal. The analog-to-digital converter is adapted to convert the analog signal to a digital signal whose value is proportional the difference between the occurrence of the detected edge of the oscillating signal and the edge of the reference clock signal.