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    HARDWARE IMPLEMENTATION OF A TEMPORAL MEMORY SYSTEM
    1.
    发明公开
    HARDWARE IMPLEMENTATION OF A TEMPORAL MEMORY SYSTEM 审中-公开
    硬件实现时间存储系统

    公开(公告)号：EP3273390A3

    公开(公告)日：2018-02-28

    申请号：EP17181762.0

    申请日：2017-07-17

    申请人： IMEC vzw

    发明人： DEGRAEVE, Robin ,  RODOPOULOS, Dimitrios

    IPC分类号： G06N3/063 ,  G06N3/04

    CPC分类号： G06N3/049 ,  G06F12/0207 ,  G06F2212/1016 ,  G06N3/0445 ,  G06N3/0454 ,  G06N3/0472 ,  G06N3/0635 ,  G06N3/08

    摘要： A hardware implementation of a temporal memory system (10) comprises
    - at least one array (360, 361, 362) of memory cells (40) logically organized in rows and columns, each memory cell being adapted for storing a scalar value and adapted for changing, e.g. for incrementing or decrementing, the stored scalar value,
    - an input system (340) adapted for receiving an input frame as input and for creating a representation for that input, which is fit for memory cell addressing in the at least one array,
    - at least one addressing unit for identifying a memory cell in the at least one array with a row address and a column address, the at least one addressing unit comprising
    - a column addressing unit (41) for receiving the representation or a derivative thereof as input and applying the representation or the derivative as a column address to the array of cells, and
    - a row addressing unit (42) for receiving a delayed version of the representation at a specified time in the past as input, and applying this representation as a row address to the array of cells,

    - a reading unit (43) adapted for reading out scalar values from a selected row of memory cells in the array, based on the row address applied, each read out scalar value corresponding to a likelihood of temporal coincidence between the input representation of the row address and the input representation of the column address, this likelihood being adjustable through the scalar value stored in the memory cell.

    摘要翻译： 时间存储器系统（10）的硬件实现包括 - 逻辑上按行和列组织的至少一个存储器单元（40）的阵列（360,361,362），每个存储器单元适于存储标量值并适用于 改变，例如 用于递增或递减所存储的标量值; - 输入系统（340），其适于接收输入帧作为输入并且用于创建适合于所述至少一个阵列中的存储器单元寻址的那个输入的表示; - 在 至少一个寻址单元，用于识别具有行地址和列地址的所述至少一个阵列中的存储器单元，所述至少一个寻址单元包括：列寻址单元（41），用于接收所述表示或其导数作为输入;以及列寻址单元 将所述表示或所述导数作为列地址应用于所述单元阵列，以及 - 行寻址单元（42），用于在过去的指定时间接收所述表示的延迟版本作为输入，并且将该表示应用为行 地址提供给单元阵列; - 读取单元（43），适于基于所施加的行地址从阵列中的选定行中的存储器单元读出标量值，每个读出的标量值对应于 行地址的输入表示与列地址的输入表示之间的时间重合的可能性，该可能性可通过存储在存储单元中的标量值进行调整。

    ELECTRONIC SYNAPSES FOR REINFORCEMENT LEARNING
    3.
    发明公开
    ELECTRONIC SYNAPSES FOR REINFORCEMENT LEARNING 有权
    电子突触获得学习

    公开(公告)号：EP2641214A1

    公开(公告)日：2013-09-25

    申请号：EP11772957.4

    申请日：2011-10-18

    申请人： International Business Machines Corporation

    发明人： MODHA, Dharmendra, Shantilal ,  CHANG, Leland ,  MONTOYE, Robert, Kevin

    IPC分类号： G06N3/063

    CPC分类号： G06N3/08 ,  G06N3/063 ,  G06N3/0635 ,  G11C11/54

    摘要： Embodiments of the invention provide electronic synapse devices for reinforcement learning. An electronic synapse is configured for interconnecting a pre-synaptic electronic neuron and a post-synaptic electronic neuron. The electronic synapse comprises memory elements configured for storing a state of the electronic synapse and storing meta information for updating the state of the electronic synapse. The electronic synapse further comprises an update module configured for updating the state of the electronic synapse based on the meta information in response to an update signal for reinforcement learning. The update module is configured for updating the state of the electronic synapse based on the meta information, in response to a delayed update signal for reinforcement learning based on a learning rule.

    CNN UNIVERSAL MACHINE AND SUPERCOMPUTER
    8.
    发明授权
    CNN UNIVERSAL MACHINE AND SUPERCOMPUTER 失效
    UNIVERSAL神经元网络中的计算机和超级计算机

    公开(公告)号：EP0664908B1

    公开(公告)日：2001-07-11

    申请号：EP94913427.4

    申请日：1993-09-23

    申请人： The Regents of the University of California

    发明人： ROSKA, Tamas ,  CHUA, Leon O.

    IPC分类号： G06N3/04 ,  G06N3/06 ,  G06G7/60

    CPC分类号： G06N3/04 ,  G06N3/0635

    摘要： This invention has 3 parts. Part 1 proposes a Cellular Neural Network or CNN universal chip (100) architecture with analog stored programs (104, 112) and time-multiplex templates. Hundreds of dedicated CNN chips may be replaced with a single programmable, real-time VLSI chip (100). Each chip (100) includes a global analogic programming unit or GAPU (102). Each chip (100) also includes a grid of enhanced cells (110), with each such cell having local units for: memory (112, 114), logic (116), communications and control (118) and output (120) functions. Part 2 proposes a unique wireless non-optical method for outputting information from the CNN analog array via electromagnetic waves generated by non-linear oscillations and chaos. Part 3 combines a set of analog, or digitally emulated, CNN universal chips (100) to design a CNN array supercomputer capable of solving non-linear partial differential equations (e.g., wave type, Navier-Stokes-type, etc.).