利索-全球专利检索

  1. 登录
  2. 注册

搜索结果

3 条记录 (耗时 0.008 秒)

    TRANSISTORS CONFIGURED FOR GATE OVERBIASING AND CIRCUITS THEREFROM
    2.
    发明公开
    TRANSISTORS CONFIGURED FOR GATE OVERBIASING AND CIRCUITS THEREFROM 审中-公开
    设置栅极过度偏置的晶体管及其电路

    公开(公告)号：EP3269039A1

    公开(公告)日：2018-01-17

    申请号：EP16708533.1

    申请日：2016-02-12

    申请人： Qualcomm Incorporated

    发明人： LOKE, Alvin Leng Sun ,  YU, Bo ,  THILENIUS, Stephen Clifford ,  JALILIZEINALI, Reza ,  ISAKANIAN, Patrick

    IPC分类号： H03K19/003 ,  H03K19/0185

    CPC分类号： H03K17/0822 ,  H03K19/00315 ,  H03K19/018521

    摘要： An electronic circuit and methods of operating the electronic circuit are provided. The electronic circuit includes a pull-up transistor for pulling up an input/output (I/O) node of the output circuit to a first voltage and a first isolation transistor for coupling the pull-up transistor to the I/O node. The electronic circuit also includes a pull-down transistor for pulling down the I/O node to a second voltage and a second isolation transistor for coupling the pull-down transistor to the I/O node. In the electronic circuit, the pull-up and the pull-down transistors are transistors supporting a first drain-to-source voltage and a first gate-to-source voltage, while the first and the second isolation transistors are transistors supporting the first drain-to-source voltage and a second gate-to-source voltage greater than the first gate-to-source voltage.