Abstract:
A pulse-width-modulated digital-to-analog converter (10) is responsive to a digital control value (35) for switching between a high gain mode and a low gain mode. The converter includes a free-running rollover counter (45), a reference register (55) and a comparator (60). Pulses from a comparator are split into two paths, one path including a switch (20), and fed into a plurality of resistive elements connected to a common output node (91). Depending on the state of the switch, the network's output value will either follow its input or be a fraction thereof, without change of duty cycle or output impedance. The output node may be connected to a capacitive element (C1) to form a low pass filter for generating an analog waveform.
Abstract:
A method and implementing apparatus for recovering data from a rotating data storage disk (10) in the presence of thermal asperities (TA) induced in a magnetoresistive transducer (18) comprises: electrically detecting a thermal asperity (TA) in a disk drive read channel (110), correlating the detected thermal asperity (TA) to a known format of the track (12), selecting at least one of a plurality of thermal asperity data recovery modes based upon the location of the thermal asperity (TA) in the formatted track (12) and applying the selected at least one of the plurality of available thermal asperity recovery modes to recover data otherwise rendered unavailable by the thermal asperity (TA).
Abstract:
A pulse width modulated digital-to-analog converter having a digital-to-analog pulse generator for outputting width modulated pulses in accordance with a digital control value. The generator includes a clock (14) for generating a clocking signal, a counter (12) responsive to the clocking signal for generating repeating sequences of N-bit counts, each sequence representing a count interval, and a bit rotator (20) for receiving the sequences of N-bit counts and for rotating bit position of at least a most significant one of N-bits. A latch (24) holds the digital control value for comparison in the comparator (22) to each one of the rotated N-bit counts to output the width modulated pulses during the count interval.
Abstract:
An analog to digital converter circuit (20) in a sampling data detection channel of a disk drive synchronously samples user data in a data track areas at a first quantization resolution and samples servo bursts from the spoke areas at a second quantization resolution effectively greater than said first quantization resolution. An offset circuit (60) provides a predetermined analog offset signal to a combining circuit (160, 170) which combines it with an incoming analog signal to provide a composite signal during a servo burst sampling interval. An analog to digital converter (180, 190) samples the composite signal during the servo spoke burst sampling interval, and synchronously samples the analog signal during a user data sampling interval. A digital averaging circuit (210) averages the servo spoke samples over a predetermined averaging interval to provide averaged burst samples having increased bit resolution.
Abstract:
A disk in a disk drive has radial spokes (14) wherein servo bursts are recorded, and multiple concentric bands (20) holding data blocks (16) in predefined block frames (22). To maximize data density, the data rate in each band (20) is proportional to the band radius, and the ratio of block frames (22) to spokes (14) in a given band (20) may be non-integral. In such bands (20), some data blocks (16) are split by a spoke (14). A disk controller in the disk drive uses a byte position accumulator (BPA) (84) when splitting a data block (16). During the transfer of a data block (16), the BPA (84) counts at the nominal data transfer rate to continually identify by its position in the data block (16) a byte therein to be transferred shortly. The BPA (84) output feeds a latch which is normally open to receive the BPA output. A timer (64) within the disk controller establishes the rotational time at which the data transfer must be suspended to avoid a spoke (14). The timer (64) generates an early warning signal (EW2) in advance of this time which closes the latch (88). The value in the closed latch (88) is the position of the last data byte to be transferred before the split. A comparator (82) indicates when a count of bytes transferred has reached the value in the latch (88); the data transfer is then suspended until the spoke (14) has passed.