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公开(公告)号:EP4457987A1
公开(公告)日:2024-11-06
申请号:EP22840320.0
申请日:2022-12-21
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公开(公告)号:EP4456434A1
公开(公告)日:2024-10-30
申请号:EP23176552.0
申请日:2023-05-31
摘要: CT ADCs based on continuous-time residue generation systems require accurate estimation of analog transfer functions. This is done by using a pseudo random bit sequence, injected using a DAC, that traverses the transfer function to be measured. Mismatch in the injection DAC introduces errors in the transfer function estimation and results in poor NSD at the ADC output. Techniques are described to improve the accuracy of the transfer function estimate despite DAC mismatch and despite the presence of an input signal.
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公开(公告)号:EP4449134A1
公开(公告)日:2024-10-23
申请号:EP22844667.0
申请日:2022-12-09
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公开(公告)号:EP4004657B1
公开(公告)日:2024-09-04
申请号:EP20754092.3
申请日:2020-07-22
IPC分类号: G05B19/042 , H03M1/06
CPC分类号: H03M1/06 , G05B19/042
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公开(公告)号:EP4391388A9
公开(公告)日:2024-08-07
申请号:EP22879792.4
申请日:2022-03-21
发明人: CHEN, Xiao
IPC分类号: H03M1/10
CPC分类号: H03M1/10 , H03M1/12 , H03M1/164 , H03M1/1215
摘要: Provided in the present application are an analog-to-digital converter and an inter-stage gain calibration method. The analog-to-digital converter comprises a sampling and holding circuit, which is configured to periodically sample and hold an analog input signal; a first-stage analog-to-digital sub-converter, which is configured to convert the analog input signal into a first digital signal, convert the first digital signal into a first voltage signal, and process a difference between the analog input signal and the first voltage signal, so as to obtain a second voltage signal; a first processing circuit, which is configured to perform clock synchronization and period delay on the first digital signal, so as to obtain a second digital signal; an inter-stage amplifier, which is realized by using an open-loop structure, and is configured to amplify the second voltage signal to obtain a third voltage signal; a second-stage analog-to-digital sub-converter, which is configured to convert the third voltage signal into a third digital signal; a second processing circuit, which is configured to perform clock synchronization on the third digital signal, so as to obtain a fourth digital signal; and an adder, which is configured to combine and add the second digital signal as a high-bit codeword and the fourth digital signal as a low-bit codeword, so as to obtain a digital output signal.
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公开(公告)号:EP4399534A1
公开(公告)日:2024-07-17
申请号:EP22867919.7
申请日:2022-08-31
IPC分类号: G01R31/3177 , H01P5/16 , H03M1/10
CPC分类号: H03M1/1009 , H03M1/12
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