公开(公告)号：EP3332345A1

公开(公告)日：2018-06-13

申请号：EP16747952.6

申请日：2016-07-25

申请人： Qualcomm Incorporated

发明人： SHARP, Colin Christopher ,  VISWANATHAN, Ramesh

IPC分类号： G06F21/10

摘要： This disclosure proposes techniques for graphics processing. In one example, a graphics processing unit (GPU) is configured to access a memory according to one of an unsecure mode and a secure mode. The GPU may include a memory access controller configured to direct memory transactions from at least one hardware unit of the GPU to a secure context bank in a memory controller when the GPU is operating in a secure mode, and configured to direct memory transactions from the at least one hardware unit of the GPU to an unsecure context bank in the memory controller when the GPU is operating in the unsecure mode.

公开(公告)号：EP3049939A1

公开(公告)日：2016-08-03

申请号：EP14772487.6

申请日：2014-08-27

申请人： Qualcomm Incorporated

发明人： GOTWALT, David A. ,  FRISINGER, Thomas Edwin ,  GRUBER, Andrew Evan ,  DEMERS, Eric ,  SHARP, Colin Christopher

IPC分类号： G06F12/08 ,  G06F12/10 ,  G06T1/60 ,  G06T15/04 ,  G06T11/00

CPC分类号： G06F12/1009 ,  G06F12/08 ,  G06F2212/302 ,  G06T1/60

摘要： The present disclosure provides for systems and methods to process a non-resident page that may include attempting to access the non-resident page, an address for the non-resident page pointing to a memory page containing default values, determining that the non-resident page should not cause a page fault based on an indicator indicating that a particular non-resident page should not generate a page fault, returning an indication that a memory read did not translate and returning the default value when the access of the non-resident page is a read and the non-resident page should not cause a page fault. Another example may discontinue a write when the access of the non-resident page is a write and the non-resident page should not cause a page fault.

公开(公告)号：EP3332346A1

公开(公告)日：2018-06-13

申请号：EP16747953.4

申请日：2016-07-25

申请人： Qualcomm Incorporated

发明人： SHARP, Colin Christopher ,  VISWANATHAN, Ramesh

IPC分类号： G06F21/10

CPC分类号： G06F21/6218 ,  G06F3/0622 ,  G06F3/0634 ,  G06F3/0673 ,  G06F21/10 ,  G06T1/20 ,  G06T1/60 ,  G06T2200/28

摘要： This disclosure proposes techniques for graphics processing. In one example, a graphics processing unit (GPU) is configured to access a memory according to one of an unsecure mode and a secure mode. The GPU may include a memory access controller configured to direct memory transactions from at least one hardware unit of the GPU to an unsecure memory unit or a secure memory unit based on the unsecure mode or secure mode and a resource descriptor associated with a memory resource.

公开(公告)号：EP2875486A1

公开(公告)日：2015-05-27

申请号：EP13735503.8

申请日：2013-06-20

申请人： Qualcomm Incorporated

发明人： METZ, Eduardus A. ,  POOLE, Nigel Terence ,  SHARP, Colin Christopher ,  GRUBER, Andrew

IPC分类号： G06T1/20 ,  G06F9/48

CPC分类号： G06F9/4806 ,  G06F9/461 ,  G06F9/4812 ,  G06T1/20

摘要： This disclosure is directed to deferred preemption techniques for scheduling graphics processing unit (GPU) command streams for execution on a GPU. A host CPU is described that is configured to control a GPU to perform deferred-preemption scheduling. For example, a host CPU may select one or more locations in a GPU command stream as being one or more locations at which preemption is allowed to occur in response to receiving a preemption notification, and may place one or more tokens in the GPU command stream based on the selected one or more locations. The tokens may indicate to the GPU that preemption is allowed to occur at the selected one or more locations. This disclosure further describes a GPU configured to preempt execution of a GPU command stream based on one or more tokens placed in a GPU command stream.

公开(公告)号：EP3201872A1

公开(公告)日：2017-08-09

申请号：EP15771408.0

申请日：2015-09-16

申请人： Qualcomm Incorporated

发明人： KOTTILINGAL, Sudeep Ravi ,  KHAN, Moinul ,  SHARP, Colin Christopher

IPC分类号： G06T1/20

CPC分类号： G06T1/60 ,  G06F12/1036 ,  G06F12/109 ,  G06F2212/657 ,  G06T1/20 ,  G06T2200/28

摘要： A transparent format converter (TFC) may determine that a request by at least one processor for graphics data stored in graphics memory is indicative of a request for graphics data in a first data format. The TFC may retrieve the graphics data in a second data format from the graphics memory based at least in part on the request for the graphics data in the graphics memory. The TFC may convert the retrieved graphics data from the second data format to the first data format. The TFC may store the converted graphics data in the first data format into a memory that is accessible by the at least one processor.

摘要翻译： 透明格式转换器（TFC）可以确定至少一个处理器对存储在图形存储器中的图形数据的请求指示对第一数据格式的图形数据的请求。 TFC可以至少部分地基于对图形存储器中的图形数据的请求从图形存储器检索第二数据格式的图形数据。 TFC可以将检索到的图形数据从第二数据格式转换为第一数据格式。 TFC可以将经转换的图形数据以第一数据格式存储到可由至少一个处理器访问的存储器中。

公开(公告)号：EP2875486B1

公开(公告)日：2016-09-14

申请号：EP13735503.8

申请日：2013-06-20

申请人： Qualcomm Incorporated

发明人： METZ, Eduardus A. ,  POOLE, Nigel Terence ,  SHARP, Colin Christopher ,  GRUBER, Andrew

IPC分类号： G06T1/20 ,  G06F9/48

CPC分类号： G06F9/4806 ,  G06F9/461 ,  G06F9/4812 ,  G06T1/20

摘要： This disclosure is directed to deferred preemption techniques for scheduling graphics processing unit (GPU) command streams for execution on a GPU. A host CPU is described that is configured to control a GPU to perform deferred-preemption scheduling. For example, a host CPU may select one or more locations in a GPU command stream as being one or more locations at which preemption is allowed to occur in response to receiving a preemption notification, and may place one or more tokens in the GPU command stream based on the selected one or more locations. The tokens may indicate to the GPU that preemption is allowed to occur at the selected one or more locations. This disclosure further describes a GPU configured to preempt execution of a GPU command stream based on one or more tokens placed in a GPU command stream.

公开(公告)号：EP3332345B1

公开(公告)日：2020-03-11

申请号：EP16747952.6

申请日：2016-07-25

申请人： Qualcomm Incorporated

发明人： SHARP, Colin Christopher ,  VISWANATHAN, Ramesh

IPC分类号： G06F21/10 ,  G06F21/74 ,  G06T1/20 ,  G06T1/60 ,  G06F12/14

公开(公告)号：EP3134864A1

公开(公告)日：2017-03-01

申请号：EP15721424.8

申请日：2015-04-21

申请人： Qualcomm Incorporated

发明人： BALCI, Murat ,  SEETHARAMAIAH, Avinash ,  FRASCATI, Christopher Paul ,  NAGENDRA KUMAR, Jonnala Gadda ,  SHARP, Colin Christopher ,  GARCIA GARCIA, David Rigel

IPC分类号： G06T1/20

CPC分类号： G06T1/20 ,  G06T1/60 ,  G06T11/40 ,  G09G5/00 ,  G09G2330/021

摘要： A device comprising a graphics processing unit (GPU) includes a memory and at least one processor. The at least one processor may be configured to: receive a GPU command packet that indicates the GPU may select between a direct rendering mode or a binning rendering mode for a portion of a frame to be rendered by the GPU, determine whether to use the direct rendering mode or the binning rendering mode for the portion of the frame to be rendered by the GPU based on at least one of: information in the received command packet or a state of the GPU, and render the portion of the frame using the determined direct rendering mode or the binning rendering mode.

摘要翻译： 包括图形处理单元（GPU）的设备包括存储器和至少一个处理器。 所述至少一个处理器可以被配置为：接收指示GPU可以在用于由GPU渲染的帧的一部分的直接呈现模式或混合渲染模式之间选择的GPU命令分组，确定是否使用直接 根据所接收的命令包中的信息或GPU的状态中的至少一个，由GPU呈现的帧的部分的再现模式或合并渲染模式，并且使用所确定的直接来渲染帧的该部分 渲染模式或分箱渲染模式。

公开(公告)号：EP2880540A1

公开(公告)日：2015-06-10

申请号：EP13745243.9

申请日：2013-07-18

申请人： Qualcomm Incorporated

发明人： SHARP, Colin Christopher ,  SARTORIUS, Thomas Andrew

IPC分类号： G06F12/10 ,  G06F12/14

CPC分类号： G06F12/1009 ,  G06F12/145 ,  G06F2212/656 ,  Y02D10/13

摘要： A first processing unit and a second processing unit can access a system memory that stores a common page table that is common to the first processing unit and the second processing unit. The common page table can store virtual memory addresses to physical memory addresses mapping for memory chunks accessed by a job of an application. A page entry, within the common page table, can include a first set of attribute bits that defines accessibility of the memory chunk by the first processing unit, a second set of attribute bits that defines accessibility of the same memory chunk by the second processing unit, and physical address bits that define a physical address of the memory chunk.