公开(公告)号：EP2956948B1

公开(公告)日：2019-12-18

申请号：EP14706428.1

申请日：2014-02-07

Applicant: Qualcomm Incorporated

Inventor： DOYLE, James Thomas ,  MAHMOUDI, Farsheed ,  SHAYAN ARANI, Amirali

IPC: H01F17/00 ,  H01F27/28 ,  H01L23/64 ,  H01L25/10

公开(公告)号：EP3345292A1

公开(公告)日：2018-07-11

申请号：EP16753748.9

申请日：2016-07-22

Applicant: Qualcomm Incorporated

Inventor： MAHMOUDI, Farsheed ,  DOYLE, James Thomas ,  SHAYAN ARANI, Amirali

IPC: H02M1/36 ,  H02M3/156 ,  H02M3/335

CPC classification number: H02M3/157 ,  H02M1/36 ,  H02M3/156 ,  H02M3/33507 ,  H02M2001/0003 ,  H02M2001/0025 ,  H02M2001/0035 ,  Y02B70/16

Abstract: A switch-mode power supply is provided that includes a comparator for producing a pulse-width modulated (PWM) controller clock signal for controlling a power switch in the switch-mode power supply. The switch-mode power supply is configured to superimpose a DC-free version of a ramp voltage with an error voltage to produce a combined voltage. The comparator compares the combined voltage to a reference voltage to produce the PWM controller clock signal.

公开(公告)号：EP3210292A1

公开(公告)日：2017-08-30

申请号：EP15778468.7

申请日：2015-09-24

Applicant: Qualcomm Incorporated

Inventor： ZHANG, Chuang ,  DOYLE, James Thomas ,  MAHMOUDI, Farsheed ,  SHAYAN ARANI, Amirali

IPC: H02M3/158 ,  H02M7/483

CPC classification number: H02M3/158 ,  H02M1/126 ,  H02M3/07 ,  H02M7/483 ,  H02M2003/072

Abstract: A circuit including: a control system for a three-level buck converter, the three-level buck converter including multiple input switches, each of the input switches receiving one of a plurality of different pulse width modulated signals, the control system including: a first clock signal and a second clock signal, the second clock signal being a phase-shifted version of the first clock signal; ramp generating circuitry receiving the first and second clock signals and producing first and second ramp signals, respectively, from the first and second clock signals; a first comparing circuit receiving the first ramp signal and producing a first one of the pulse width modulated signals therefrom; and a second comparing circuit receiving the second ramp signal and producing a second one of the pulse width modulated signals therefrom.

Abstract translation: 一种电路，包括：用于三电平降压转换器的控制系统，所述三电平降压转换器包括多个输入开关，每个所述输入开关接收多个不同的脉宽调制信号中的一个，所述控制系统包括：第一 时钟信号和第二时钟信号，所述第二时钟信号是所述第一时钟信号的相移版本; 斜坡产生电路，用于接收第一和第二时钟信号并分别从第一和第二时钟信号产生第一和第二斜坡信号; 第一比较电路，用于接收第一斜坡信号并从其产生第一脉宽调制信号; 以及第二比较电路，接收第二斜坡信号并由此产生第二个脉宽调制信号。

公开(公告)号：EP2956948A1

公开(公告)日：2015-12-23

申请号：EP14706428.1

申请日：2014-02-07

Applicant: Qualcomm Incorporated

Inventor： DOYLE, James Thomas ,  MAHMOUDI, Farsheed ,  SHAYAN ARANI, Amirali

IPC: H01F27/28

Abstract: Some novel features pertain to an in-substrate inductor structure that includes a first inductor winding, a second inductor winding and a substrate. The first inductor winding includes an electrically conductive material. The second inductor winding includes an electrically conductive material. The substrate is laterally located between the first inductor winding and the second inductor winding. The substrate is configured to provide structural coupling of the first and second inductor windings. In some implementations, the first inductor winding is laterally co-planar to the second inductor winding. In some implementations, the first inductor winding has a first spiral shape and the second inductor winding has a second spiral shape. In some implementations, the first inductor winding and the second inductor winding have an elongated circular shape. In some implementations, the substrate is a silicon substrate.

Abstract translation: 一些新颖的特征涉及内置电感器结构，其包括第一电感器绕组，第二电感器绕组和衬底。 第一电感线圈包括导电材料。 第二电感线圈包括导电材料。 衬底横向位于第一电感器绕组和第二电感器绕组之间。 衬底被配置为提供第一和第二电感器绕组的结构耦合。 在一些实施方案中，第一电感器绕组与第二电感器绕组横向共面。 在一些实施方案中，第一电感器绕组具有第一螺旋形状，并且第二电感器绕组具有第二螺旋形状。 在一些实施方案中，第一电感器绕组和第二电感器绕组具有细长的圆形形状。 在一些实施方式中，衬底是硅衬底。

公开(公告)号：EP3210288B1

公开(公告)日：2018-12-05

申请号：EP15781795.8

申请日：2015-09-24

Applicant: Qualcomm Incorporated

Inventor： ZHANG, Chuang ,  DOYLE, James, Thomas ,  MAHMOUDI, Farsheed ,  SHAYAN ARANI, Amirali

IPC: H02M1/12 ,  H02M3/07 ,  H02M7/483 ,  H03H7/01

CPC classification number: H02M3/158 ,  H02M1/14 ,  H02M7/483 ,  H02M2003/072

Abstract: A circuit including: a three-level buck converter having: a plurality of input switches and an inductor configured to receive a voltage from the plurality of input switches, the plurality of input switches coupled with a first capacitor and configured to charge and discharge the first capacitor; a second capacitor at an output of the buck converter; and a switched capacitor at an input node of the inductor, wherein the switched capacitor is smaller than either the first capacitor or the second capacitor.

公开(公告)号：EP3210288A1

公开(公告)日：2017-08-30

申请号：EP15781795.8

申请日：2015-09-24

Applicant: Qualcomm Incorporated

Inventor： ZHANG, Chuang ,  DOYLE, James, Thomas ,  MAHMOUDI, Farsheed ,  SHAYAN ARANI, Amirali

IPC: H02M1/12 ,  H02M3/07 ,  H02M7/483 ,  H03H7/01

CPC classification number: H02M3/158 ,  H02M1/14 ,  H02M7/483 ,  H02M2003/072

Abstract: A circuit including: a three-level buck converter having: a plurality of input switches and an inductor configured to receive a voltage from the plurality of input switches, the plurality of input switches coupled with a first capacitor and configured to charge and discharge the first capacitor; a second capacitor at an output of the buck converter; and a switched capacitor at an input node of the inductor, wherein the switched capacitor is smaller than either the first capacitor or the second capacitor.

Abstract translation: 一种电路，包括：三电平降压转换器，具有：多个输入开关和电感器，所述多个输入开关和电感器被配置为从所述多个输入开关接收电压，所述多个输入开关与第一电容器耦合并且被配置为对所述第一电容器 电容器; 在降压转换器的输出处的第二电容器; 以及在所述电感器的输入节点处的开关电容器，其中所述开关电容器小于所述第一电容器或所述第二电容器。