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1.发明授权
公开(公告)号：EP2997459B1
公开(公告)日：2018-03-07
申请号：EP14730327.5
申请日：2014-05-09
CPC分类号： G06F12/0246 , G06F2212/7201 , G06F2212/7203
摘要： Aspects include systems and methods for increasing performance of a flash translation layer (FTL) of a flash memory device. A copy of FTL tables stored on a flash memory device may be copied to a memory of a host device. The copy of the FTL tables may be directly accessed by the flash memory device to translate between logical addresses provided by the host device for read/write operations from/to a flash memory of the flash memory device, and the respective physical addresses of the flash memory. The flash memory device is granted direct memory access to a portion of the memory of the host device where the copy of the FTL tables is stored. The flash memory device bus masters communication busses connecting the flash memory device to the memory of the host device.
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2.发明公开WIDE INPUT OUTPUT MEMORY WITH LOW DENSITY, LOW LATENCY AND HIGH DENSITY, HIGH LATENCY BLOCKS 审中-公开具有低密度和低延时积木块和高密度和高延迟宽输入输出存储器
公开(公告)号：EP2609622A2
公开(公告)日：2013-07-03
申请号：EP11754577.2
申请日：2011-08-24
IPC分类号： H01L23/48 , G11C11/4076
CPC分类号： G11C11/4076 , H01L23/481 , H01L24/73 , H01L25/0657 , H01L2224/16145 , H01L2224/16225 , H01L2224/32145 , H01L2224/32225 , H01L2224/48227 , H01L2224/73204 , H01L2224/73265 , H01L2225/0651 , H01L2225/06513 , H01L2225/06517 , H01L2225/06541 , H01L2225/06568 , H01L2924/10253 , H01L2924/14 , H01L2924/15311 , H01L2924/00012 , H01L2924/00
摘要： External memory having a high density, high latency memory block; and a low density, low latency memory block. The two memory blocks may be separately accessed by one or more processing functional units. The access may be a direct memory access, or by way of a bus or fabric switch. Through-die vias may connect the external memory to a die comprising the one or more processing functional units.
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3.发明公开
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4.发明公开
公开(公告)号：EP2997459A1
公开(公告)日：2016-03-23
申请号：EP14730327.5
申请日：2014-05-09
CPC分类号： G06F12/0246 , G06F2212/7201 , G06F2212/7203
摘要： Aspects include systems and methods for increasing performance of a flash translation layer (FTL) of a flash memory device. A copy of FTL tables stored on a flash memory device may be copied to a memory of a host device. The copy of the FTL tables may be directly accessed by the flash memory device to translate between logical addresses provided by the host device for read/write operations from/to a flash memory of the flash memory device, and the respective physical addresses of the flash memory. The flash memory device is granted direct memory access to a portion of the memory of the host device where the copy of the FTL tables is stored. The flash memory device bus masters communication busses connecting the flash memory device to the memory of the host device.
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