BAND-GAP CURRENT REPEATER
    1.
    发明公开
    BAND-GAP CURRENT REPEATER 审中-公开
    BANDABSTAND-STROM中继器

    公开(公告)号:EP3132325A1

    公开(公告)日:2017-02-22

    申请号:EP15711032.1

    申请日:2015-03-11

    IPC分类号: G05F3/30

    摘要: A series of current repeaters with localized feedback is provided. Each current that precedes a subsequent current repeater in the series is configured to receive a feedback current from the subsequent current repeater and generate an error signal accordingly with a differential amplifier so as to reduce current repetition errors that would otherwise result from an offset voltage in the differential amplifier.

    摘要翻译: 提供了具有局部反馈的一系列电流中继器。 在串联中的随后的当前中继器之前的每个电流被配置为从随后的当前中继器接收反馈电流并且相应地使用差分放大器生成误差信号,以便减少否则由于 差分放大器。

    SYSTEMS AND METHODS FOR FREQUENCY DETECTION
    4.
    发明公开
    SYSTEMS AND METHODS FOR FREQUENCY DETECTION 有权
    SYSTEME UND VERFAHREN ZUR FREQUENZDETEKTION

    公开(公告)号:EP3114805A1

    公开(公告)日:2017-01-11

    申请号:EP15707228.1

    申请日:2015-02-18

    IPC分类号: H04L25/02 H04L25/49

    CPC分类号: H04L25/0262 H04L25/4902

    摘要: Methods and systems according to one or more embodiments are provided for frequency detection. In an embodiment, a frequency detector is provided that includes a capacitor that discharges or charges responsive to binary states of an input signal.

    摘要翻译: 提供了根据一个或多个实施例的方法和系统用于频率检测。 在一个实施例中,提供了一种频率检测器,其包括响应于输入信号的二进制状态而放电或充电的电容器。

    RE-TIMING BASED CLOCK GENERATION AND RESIDUAL SIDEBAND (RSB) ENHANCEMENT CIRCUIT

    公开(公告)号:EP3513494A2

    公开(公告)日:2019-07-24

    申请号:EP17777700.0

    申请日:2017-09-13

    IPC分类号: H03K5/156 H03K21/02

    摘要: Certain aspects of the present disclosure generally relate to methods and apparatus for generating clock signals. For example, certain aspects of the present disclosure provide a clock generation circuit. The clock generation circuit may include a first transistor connected in cascode with a second transistor, wherein an input clock node of the circuit is coupled to gates of the first and second transistors. The clock generation circuit may also include a frequency divider circuit having an input coupled to the input clock node, wherein an output of the frequency divider circuit is coupled to a source of the second transistor, and wherein an output node of the circuit is coupled to drains of the first and second transistors.