公开(公告)号：EP0287337A3

公开(公告)日：1989-07-26

申请号：EP88303292.2

申请日：1988-04-13

申请人： ROHM CORPORATION

发明人： Goetting, Erich

IPC分类号： H03K19/177

CPC分类号： H03K19/17772 ,  H03K17/22 ,  H03K19/17704 ,  H03K19/17744 ,  H03K19/1776

摘要： An improved architecture for programming an output cell (macro cell) in a PLD. The memory cells for the macro cell (18) are stored in the main array (10) itself. Upon power-up, a power-on sense circuit (40) senses the presence of power and enables an architecture portion (14) of the main array (10) while disabling the rest (12) of the main array (10). The power-on sense signal (POS) also enables a path from the output of the array to the macro cell elements (18) to be programmed. When the power-on sense signal (POS) is removed a short time after power-up, this path is blocked so that the array outputs continue on their normal path and the architecture portion (14) of the array (10) is disabled while the rest (12) of the array (10) is enabled for normal operation.

公开(公告)号：EP0287338B1

公开(公告)日：1992-08-05

申请号：EP88303293.0

申请日：1988-04-13

申请人： ROHM CORPORATION

发明人： Goetting, Erich

IPC分类号： H03K19/177

CPC分类号： H03K19/17764 ,  G11C7/24 ,  G11C16/22 ,  H03K19/17708

公开(公告)号：EP0287338A2

公开(公告)日：1988-10-19

申请号：EP88303293.0

申请日：1988-04-13

申请人： ROHM CORPORATION

发明人： Goetting, Erich

IPC分类号： H03K19/177

CPC分类号： H03K19/17764 ,  G11C7/24 ,  G11C16/22 ,  H03K19/17708

摘要： One of the programmable elements of the array (20) is designated as a security element (22), and its output is coupled to a latching mechanism (30). The output of the latching mechanism (30) is coupled to a mechanism (36) for disabling the read output of the array (20). The latching mechanism (30) is enabled for a short time by a pulse when power is applied to the circuit. Thus, when power is first applied, the security fuse (22) has not been set and the latch output will allow data to be read. While power is applied, all of the programmable elements can be set, including the security element (22). All the elements, including the security fuse (22), can then be verified by reading them out. When power is turned off and subsequently reapplied, the latch (30) will then be enabled and the set security fuse level will appear at the latch output, thereby disabling the reading out of the program data. The present invention thus allows verification of the setting of the security fuse (22) and verification of the other programmable elements after the security fuse (22) has been set.

摘要翻译： 阵列（20）的可编程元件之一被指定为安全元件（22），并且其输出端连接到锁定机构（30）。 锁定机构（30）的输出耦合到用于禁止阵列（20）的读取输出的机构（36）。 当向电路施加电力时，锁存机构（30）通过脉冲使能很短时间。 因此，当首次施加电力时，安全保险丝（22）尚未被设置并且锁存器输出将允许读取数据。 当施加电力时，可以设置所有可编程元件，包括安全元件（22）。 所有的元件，包括安全保险丝（22），然后可以通过读出来验证。 当电源关闭并随后重新应用时，锁存器（30）将被使能，并且设置的安全熔断器电平将出现在锁存器输出端，从而禁止读出程序数据。 因此，本发明允许在安全保险丝（22）被设置之后验证安全熔丝（22）的设置和其他可编程元件的验证。

公开(公告)号：EP0287337B1

公开(公告)日：1993-09-15

申请号：EP88303292.2

申请日：1988-04-13

申请人： ROHM CORPORATION

发明人： Goetting, Erich

IPC分类号： H03K19/177

CPC分类号： H03K19/17772 ,  H03K17/22 ,  H03K19/17704 ,  H03K19/17744 ,  H03K19/1776

公开(公告)号：EP0287338A3

公开(公告)日：1989-07-19

申请号：EP88303293.0

申请日：1988-04-13

申请人： ROHM CORPORATION

发明人： Goetting, Erich

IPC分类号： H03K19/177

CPC分类号： H03K19/17764 ,  G11C7/24 ,  G11C16/22 ,  H03K19/17708

摘要： One of the programmable elements of the array (20) is designated as a security element (22), and its output is coupled to a latching mechanism (30). The output of the latching mechanism (30) is coupled to a mechanism (36) for disabling the read output of the array (20). The latching mechanism (30) is enabled for a short time by a pulse when power is applied to the circuit. Thus, when power is first applied, the security fuse (22) has not been set and the latch output will allow data to be read. While power is applied, all of the programmable elements can be set, including the security element (22). All the elements, including the security fuse (22), can then be verified by reading them out. When power is turned off and subsequently reapplied, the latch (30) will then be enabled and the set security fuse level will appear at the latch output, thereby disabling the reading out of the program data. The present invention thus allows verification of the setting of the security fuse (22) and verification of the other programmable elements after the security fuse (22) has been set.

公开(公告)号：EP0287337A2

公开(公告)日：1988-10-19

申请号：EP88303292.2

申请日：1988-04-13

申请人： ROHM CORPORATION

发明人： Goetting, Erich

IPC分类号： H03K19/177

CPC分类号： H03K19/17772 ,  H03K17/22 ,  H03K19/17704 ,  H03K19/17744 ,  H03K19/1776

摘要： An improved architecture for programming an output cell (macro cell) in a PLD. The memory cells for the macro cell (18) are stored in the main array (10) itself. Upon power-up, a power-on sense circuit (40) senses the presence of power and enables an architecture portion (14) of the main array (10) while disabling the rest (12) of the main array (10). The power-on sense signal (POS) also enables a path from the output of the array to the macro cell elements (18) to be programmed. When the power-on sense signal (POS) is removed a short time after power-up, this path is blocked so that the array outputs continue on their normal path and the architecture portion (14) of the array (10) is disabled while the rest (12) of the array (10) is enabled for normal operation.

摘要翻译： 用于对PLD中的输出单元（宏单元）进行编程的改进的架构。 用于宏单元（18）的存储单元自身存储在主阵列（10）中。 在上电时，上电检测电路（40）感测到电力的存在，并使主阵列（10）的架构部分（14）能够禁用主阵列（10）的其余部分（12）。 上电感测信号（POS）还使得能够对从阵列的输出到宏小区元件（18）的路径进行编程。 当在上电后短时间内去除上电感测信号（POS）时，该路径被阻塞，使得阵列输出在其正常路径上继续运行，并且阵列（10）的架构部分（14）被禁用，而 阵列（10）的其余部分（12）启用正常操作。